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* move files to file-2.6.30Florian Fainelli2010-02-043-801/+0
| | | | SVN-Revision: 19518
* I recently came across an ar7 device which has the vlynq hardwired so that ↵Florian Fainelli2009-05-251-23/+127
| | | | | | | | | | | | | | | | the clocks are always generated by the remote device instead of the local one. Upon initialization the current version of vlynq driver disables remote clock generation and causes the entire bus to hang on my device. This patch adds support for detecting which device (local or remote) is responsible of clock generation and implements clock initialization based on detection result. Signed-off-by: Antti Seppala <a.seppala at gmail.com> SVN-Revision: 16049
* Treat vlynq external divisor just like automatic, fix comment about it, ↵Florian Fainelli2008-09-011-1/+3
| | | | | | thanks sn9 SVN-Revision: 12467
* Fix divisor calculation and configuration from previous commit, thanks sn9Florian Fainelli2008-09-011-37/+16
| | | | SVN-Revision: 12454
* Fix divisor settings for external devices like wireless devices, thanks sn9Florian Fainelli2008-08-311-13/+41
| | | | SVN-Revision: 12443
* ar7: remove unneeded packed and array initializationMatteo Croce2008-04-071-1/+1
| | | | SVN-Revision: 10752
* vlynq: small fixesMatteo Croce2008-04-021-1/+2
| | | | SVN-Revision: 10711
* add proper email addresses to the comment headersMatteo Croce2008-04-021-1/+1
| | | | SVN-Revision: 10709
* Let authors holds copyright of the AR7 code (closes #2369)Matteo Croce2008-04-021-1/+1
| | | | SVN-Revision: 10708
* vlynq: probe for an external clock first, needed to enable acx on the ↵Matteo Croce2008-04-021-9/+8
| | | | | | Leonardo board SVN-Revision: 10707
* Fix VLYNQ device enable for DG834Gv1Felix Fietkau2007-12-041-1/+1
| | | | | | | | | | | | | | | | | | | | This patch allows VLYNQ devices on the DG834Gv1 to be successfully enabled. Currently the "__vlynq_enable_device" function attempts to set the VLYNQ device clock divisor to values from 1 through 8 until a link is successfully established. On the DG834Gv1 (but not the DG834Gv2), setting the VLYNQ device clock divisor to 1 (full rate) results in all further VLYNQ operations failing (including software reset), so the device is never enabled. This patches changes the function to only attempt divisors 2 through 8, and hence the device is successfully enabled. Signed-off-by: Nick Forbes <nick.forbes@huntsworth.com> --------- SVN-Revision: 9656
* cleanup vlynq. drop vlynq-pciEugene Konev2007-10-053-0/+688
SVN-Revision: 9143
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