1 files changed, 0 insertions, 62 deletions
diff --git a/target/linux/sunxi/patches-3.14/176-clk-sun5i-add-support-for-reset-ctrler.patch b/target/linux/sunxi/patches-3.14/176-clk-sun5i-add-support-for-reset-ctrler.patch
deleted file mode 100644
index 3986d193b1..0000000000
--- a/target/linux/sunxi/patches-3.14/176-clk-sun5i-add-support-for-reset-ctrler.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 3ec31fa2ce161d35f787354037f94d9d22d825d1 Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Fri, 20 Dec 2013 22:41:08 +0100
-Subject: [PATCH] clocksource: sun5i: Add support for reset controller
-
-The Allwinner A31 that uses this timer has the timer IP asserted in reset.
-Add an optional reset property to the DT, and deassert the timer from reset if
-it's there.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- .../devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt       | 4 ++++
- drivers/clocksource/timer-sun5i.c                                   | 6 ++++++
- 2 files changed, 10 insertions(+)
-
---- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
-+++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
-@@ -9,6 +9,9 @@ Required properties:
- 		one)
- - clocks: phandle to the source clock (usually the AHB clock)
- 
-+Optionnal properties:
-+- resets: phandle to a reset controller asserting the timer
-+
- Example:
- 
- timer@01c60000 {
-@@ -19,4 +22,5 @@ timer@01c60000 {
- 		     <0 53 1>,
- 		     <0 54 1>;
- 	clocks = <&ahb1_gates 19>;
-+	resets = <&ahb1rst 19>;
- };
---- a/drivers/clocksource/timer-sun5i.c
-+++ b/drivers/clocksource/timer-sun5i.c
-@@ -16,6 +16,7 @@
- #include <linux/interrupt.h>
- #include <linux/irq.h>
- #include <linux/irqreturn.h>
-+#include <linux/reset.h>
- #include <linux/sched_clock.h>
- #include <linux/of.h>
- #include <linux/of_address.h>
-@@ -143,6 +144,7 @@ static u64 sun5i_timer_sched_read(void)
- 
- static void __init sun5i_timer_init(struct device_node *node)
- {
-+	struct reset_control *rstc;
- 	unsigned long rate;
- 	struct clk *clk;
- 	int ret, irq;
-@@ -162,6 +164,10 @@ static void __init sun5i_timer_init(stru
- 	clk_prepare_enable(clk);
- 	rate = clk_get_rate(clk);
- 
-+	rstc = of_reset_control_get(node, NULL);
-+	if (!IS_ERR(rstc))
-+		reset_control_deassert(rstc);
-+
- 	writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
- 	writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
- 	       timer_base + TIMER_CTL_REG(1));