1 files changed, 48 insertions, 0 deletions
diff --git a/target/linux/mvebu/patches-4.4/136-phylink-add-ethtool-nway_reset-support.patch b/target/linux/mvebu/patches-4.4/136-phylink-add-ethtool-nway_reset-support.patch
new file mode 100644
index 0000000000..ade904eebd
--- /dev/null
+++ b/target/linux/mvebu/patches-4.4/136-phylink-add-ethtool-nway_reset-support.patch
@@ -0,0 +1,48 @@
+From d6bd25b692378ec17bdb1023d398c03c45829947 Mon Sep 17 00:00:00 2001
+From: Russell King <rmk+kernel@arm.linux.org.uk>
+Date: Thu, 1 Oct 2015 20:27:19 +0100
+Subject: [PATCH 724/744] phylink: add ethtool nway_reset support
+
+Add ethtool nway_reset support to phylink, to allow userspace to
+request a re-negotiation of the link.
+
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+---
+ drivers/net/phy/phylink.c | 14 ++++++++++++++
+ include/linux/phylink.h   |  1 +
+ 2 files changed, 15 insertions(+)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -687,6 +687,20 @@ int phylink_ethtool_set_settings(struct
+ }
+ EXPORT_SYMBOL_GPL(phylink_ethtool_set_settings);
+ 
++int phylink_ethtool_nway_reset(struct phylink *pl)
++{
++	int ret = 0;
++
++	mutex_lock(&pl->config_mutex);
++	if (pl->phydev)
++		ret = genphy_restart_aneg(pl->phydev);
++	phylink_mac_an_restart(pl);
++	mutex_unlock(&pl->config_mutex);
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(phylink_ethtool_nway_reset);
++
+ /* This emulates MII registers for a fixed-mode phy operating as per the
+  * passed in state. "aneg" defines if we report negotiation is possible.
+  *
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -65,6 +65,7 @@ void phylink_stop(struct phylink *);
+ 
+ int phylink_ethtool_get_settings(struct phylink *, struct ethtool_cmd *);
+ int phylink_ethtool_set_settings(struct phylink *, struct ethtool_cmd *);
++int phylink_ethtool_nway_reset(struct phylink *);
+ int phylink_mii_ioctl(struct phylink *, struct ifreq *, int);
+ 
+ void phylink_set_link_port(struct phylink *pl, u32 support, u8 port);