diff options
Diffstat (limited to 'target/linux/magicbox-2.6/patches/001-magicbox_support.patch')
| -rw-r--r-- | target/linux/magicbox-2.6/patches/001-magicbox_support.patch | 308 |
1 files changed, 2 insertions, 306 deletions
diff --git a/target/linux/magicbox-2.6/patches/001-magicbox_support.patch b/target/linux/magicbox-2.6/patches/001-magicbox_support.patch index 7c609e5d02..873160d3bc 100644 --- a/target/linux/magicbox-2.6/patches/001-magicbox_support.patch +++ b/target/linux/magicbox-2.6/patches/001-magicbox_support.patch @@ -18,8 +18,8 @@ diff -urN linux.old/arch/ppc/platforms/4xx/Kconfig linux.dev/arch/ppc/platforms/ config IBM_OCP bool -- depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT -+ depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT || MAGICBOX +- depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || TAISHAN || WALNUT ++ depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || TAISHAN || WALNUT || MAGICBOX default y config IBM_EMAC4 @@ -41,310 +41,6 @@ diff -urN linux.old/arch/ppc/platforms/4xx/Kconfig linux.dev/arch/ppc/platforms/ default y config 405GP -diff -urN linux.old/arch/ppc/platforms/4xx/magicbox.c linux.dev/arch/ppc/platforms/4xx/magicbox.c ---- linux.old/arch/ppc/platforms/4xx/magicbox.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/ppc/platforms/4xx/magicbox.c 2006-12-14 08:48:56.000000000 +0100 -@@ -0,0 +1,249 @@ -+/* -+ * Support for IBM PPC 405EP-based MagicBox board -+ * Copyright (C) 2006 Karol Lewandowski -+ * -+ * Heavily based on bubinga.c -+ * -+ * Author: SAW (IBM), derived from walnut.c. -+ * Maintained by MontaVista Software <source@mvista.com> -+ * -+ * 2003 (c) MontaVista Softare Inc. This file is licensed under the -+ * terms of the GNU General Public License version 2. This program is -+ * licensed "as is" without any warranty of any kind, whether express -+ * or implied. -+ */ -+ -+#include <linux/autoconf.h> -+#include <linux/init.h> -+#include <linux/smp.h> -+#include <linux/threads.h> -+#include <linux/param.h> -+#include <linux/string.h> -+#include <linux/blkdev.h> -+#include <linux/pci.h> -+#include <linux/tty.h> -+#include <linux/serial.h> -+#include <linux/serial_core.h> -+ -+#include <asm/system.h> -+#include <asm/pci-bridge.h> -+#include <asm/processor.h> -+#include <asm/machdep.h> -+#include <asm/page.h> -+#include <asm/time.h> -+#include <asm/io.h> -+#include <asm/kgdb.h> -+#include <asm/ocp.h> -+#include <asm/ibm_ocp_pci.h> -+ -+#include <platforms/4xx/ibm405ep.h> -+ -+#undef DEBUG -+ -+#ifdef DEBUG -+#define DBG(x...) printk(x) -+#else -+#define DBG(x...) -+#endif -+ -+extern bd_t __res; -+ -+/* Some IRQs unique to board -+ * Used by the generic 405 PCI setup functions in ppc4xx_pci.c -+ */ -+int __init -+ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) -+{ -+ static char pci_irq_table[][4] = -+ /* -+ * PCI IDSEL/INTPIN->INTLINE -+ * A B C D -+ */ -+ { -+ {28, 28, 28, 28}, /* IDSEL 1 - PCI slot 1 */ -+ {29, 29, 29, 29}, /* IDSEL 2 - PCI slot 2 */ -+ {30, 30, 30, 30}, /* IDSEL 3 - PCI slot 3 */ -+ {31, 31, 31, 31}, /* IDSEL 4 - PCI slot 4 */ -+ }; -+ -+ const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; -+ return PCI_IRQ_TABLE_LOOKUP; -+}; -+ -+ -+/* The serial clock for the chip is an internal clock determined by -+ * different clock speeds/dividers. -+ * Calculate the proper input baud rate and setup the serial driver. -+ */ -+static void __init -+magicbox_early_serial_map(void) -+{ -+ u32 uart_div; -+ int uart_clock; -+ struct uart_port port; -+ -+ /* Calculate the serial clock input frequency -+ * -+ * The base baud is the PLL OUTA (provided in the board info -+ * structure) divided by the external UART Divisor, divided -+ * by 16. -+ */ -+ uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV); -+ uart_clock = __res.bi_procfreq / uart_div; -+ -+ /* Setup serial port access */ -+ memset(&port, 0, sizeof(port)); -+ port.membase = (void*)ACTING_UART0_IO_BASE; -+ port.irq = ACTING_UART0_INT; -+ port.uartclk = uart_clock; -+ port.regshift = 0; -+ port.iotype = SERIAL_IO_MEM; -+ port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; -+ port.line = 0; -+ -+ if (early_serial_setup(&port) != 0) { -+ printk("Early serial init of port 0 failed\n"); -+ } -+ -+ port.membase = (void*)ACTING_UART1_IO_BASE; -+ port.irq = ACTING_UART1_INT; -+ port.line = 1; -+ -+ if (early_serial_setup(&port) != 0) { -+ printk("Early serial init of port 1 failed\n"); -+ } -+} -+ -+void __init -+bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip) -+{ -+ unsigned int bar_response, bar; -+ /* -+ * Expected PCI mapping: -+ * -+ * PLB addr PCI memory addr -+ * --------------------- --------------------- -+ * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff -+ * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff -+ * -+ * PLB addr PCI io addr -+ * --------------------- --------------------- -+ * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000 -+ * -+ * The following code is simplified by assuming that the bootrom -+ * has been well behaved in following this mapping. -+ */ -+ -+#ifdef DEBUG -+ int i; -+ -+ printk("ioremap PCLIO_BASE = 0x%x\n", pcip); -+ printk("PCI bridge regs before fixup \n"); -+ for (i = 0; i <= 3; i++) { -+ printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma))); -+ printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la))); -+ printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila))); -+ printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha))); -+ } -+ printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms))); -+ printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la))); -+ printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms))); -+ printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la))); -+ -+#endif -+ -+ /* added for IBM boot rom version 1.15 bios bar changes -AK */ -+ -+ /* Disable region first */ -+ out_le32((void *) &(pcip->pmm[0].ma), 0x00000000); -+ /* PLB starting addr, PCI: 0x80000000 */ -+ out_le32((void *) &(pcip->pmm[0].la), 0x80000000); -+ /* PCI start addr, 0x80000000 */ -+ out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE); -+ /* 512MB range of PLB to PCI */ -+ out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000); -+ /* Enable no pre-fetch, enable region */ -+ out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff - -+ (PPC405_PCI_UPPER_MEM - -+ PPC405_PCI_MEM_BASE)) | 0x01)); -+ -+ /* Disable region one */ -+ out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); -+ out_le32((void *) &(pcip->pmm[1].la), 0x00000000); -+ out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000); -+ out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000); -+ out_le32((void *) &(pcip->pmm[1].ma), 0x00000000); -+ out_le32((void *) &(pcip->ptm1ms), 0x00000001); -+ -+ /* Disable region two */ -+ out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); -+ out_le32((void *) &(pcip->pmm[2].la), 0x00000000); -+ out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000); -+ out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000); -+ out_le32((void *) &(pcip->pmm[2].ma), 0x00000000); -+ out_le32((void *) &(pcip->ptm2ms), 0x00000000); -+ out_le32((void *) &(pcip->ptm2la), 0x00000000); -+ -+ /* Zero config bars */ -+ for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) { -+ early_write_config_dword(hose, hose->first_busno, -+ PCI_FUNC(hose->first_busno), bar, -+ 0x00000000); -+ early_read_config_dword(hose, hose->first_busno, -+ PCI_FUNC(hose->first_busno), bar, -+ &bar_response); -+ DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n", -+ hose->first_busno, PCI_SLOT(hose->first_busno), -+ PCI_FUNC(hose->first_busno), bar, bar_response); -+ } -+ /* end work arround */ -+ -+#ifdef DEBUG -+ printk("PCI bridge regs after fixup \n"); -+ for (i = 0; i <= 3; i++) { -+ printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma))); -+ printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la))); -+ printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila))); -+ printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha))); -+ } -+ printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms))); -+ printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la))); -+ printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms))); -+ printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la))); -+ -+#endif /* DEBUG */ -+} -+ -+void __init -+magicbox_setup_arch(void) -+{ -+ ppc4xx_setup_arch(); -+ -+ ibm_ocp_set_emac(0, 1); -+ -+ magicbox_early_serial_map(); -+ -+ /* Identify the system */ -+ printk("MagicBox port (C) 2005 Karol Lewandowski <kl@jasmine.eu.org>\n"); -+} -+ -+void __init -+magicbox_map_io(void) -+{ -+ ppc4xx_map_io(); -+} -+ -+void __init -+platform_init(unsigned long r3, unsigned long r4, unsigned long r5, -+ unsigned long r6, unsigned long r7) -+{ -+ ppc4xx_init(r3, r4, r5, r6, r7); -+ -+ ppc_md.setup_arch = magicbox_setup_arch; -+ ppc_md.setup_io_mappings = magicbox_map_io; -+ -+#ifdef CONFIG_KGDB -+ ppc_md.early_serial_map = bubinga_early_serial_map; -+#endif -+ -+} -diff -urN linux.old/arch/ppc/platforms/4xx/magicbox.h linux.dev/arch/ppc/platforms/4xx/magicbox.h ---- linux.old/arch/ppc/platforms/4xx/magicbox.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/ppc/platforms/4xx/magicbox.h 2006-12-14 08:48:56.000000000 +0100 -@@ -0,0 +1,47 @@ -+/* -+ * Support for IBM PPC 405EP-based MagicBox board -+ * -+ * Heavily based on bubinga.h -+ * -+ * -+ * Author: SAW (IBM), derived from walnut.h. -+ * Maintained by MontaVista Software <source@mvista.com> -+ * -+ * 2003 (c) MontaVista Softare Inc. This file is licensed under the -+ * terms of the GNU General Public License version 2. This program is -+ * licensed "as is" without any warranty of any kind, whether express -+ * or implied. -+ */ -+ -+#ifdef __KERNEL__ -+#ifndef __MAGICBOX_H__ -+#define __MAGICBOX_H__ -+ -+#include <linux/autoconf.h> -+#include <platforms/4xx/ibm405ep.h> -+#include <asm/ppcboot.h> -+ -+/* Memory map for the "MagicBox" 405EP evaluation board -- generic 4xx. */ -+ -+/* The UART clock is based off an internal clock - -+ * define BASE_BAUD based on the internal clock and divider(s). -+ * Since BASE_BAUD must be a constant, we will initialize it -+ * using clock/divider values which OpenBIOS initializes -+ * for typical configurations at various CPU speeds. -+ * The base baud is calculated as (FWDA / EXT UART DIV / 16) -+ */ -+#define BASE_BAUD 0 -+ -+/* Flash */ -+#define PPC40x_FPGA_BASE 0xF0300000 -+#define PPC40x_FPGA_REG_OFFS 1 /* offset to flash map reg */ -+#define PPC40x_FLASH_ONBD_N(x) (x & 0x02) -+#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01) -+#define PPC40x_FLASH_LOW 0xFFF00000 -+#define PPC40x_FLASH_HIGH 0xFFF80000 -+#define PPC40x_FLASH_SIZE 0x80000 -+ -+#define PPC4xx_MACHINE_NAME "MagicBox" -+ -+#endif /* __MAGICBOX_H__ */ -+#endif /* __KERNEL__ */ diff -urN linux.old/arch/ppc/platforms/4xx/Makefile linux.dev/arch/ppc/platforms/4xx/Makefile --- linux.old/arch/ppc/platforms/4xx/Makefile 2006-11-29 22:57:37.000000000 +0100 +++ linux.dev/arch/ppc/platforms/4xx/Makefile 2006-12-14 08:48:56.000000000 +0100 |