diff options
Diffstat (limited to 'target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch | 73 |
1 files changed, 32 insertions, 41 deletions
diff --git a/target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch b/target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch index bdf0d0fb69..564321c7c8 100644 --- a/target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch +++ b/target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch @@ -1,10 +1,9 @@ --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c -@@ -13,6 +13,22 @@ - #include <asm/smtc_ipi.h> - #include <asm/time.h> +@@ -15,6 +15,22 @@ + #include <asm/cevt-r4k.h> -+/* + /* + * Compare interrupt can be routed and latched outside the core, + * so a single execution hazard barrier may not be enough to give + * it time to clear as seen in the Cause register. 4 time the @@ -20,46 +19,38 @@ + irq_disable_hazard(); \ + } while (0) + - static int mips_next_event(unsigned long delta, - struct clock_event_device *evt) - { -@@ -28,6 +44,7 @@ ++/* + * The SMTC Kernel for the 34K, 1004K, et. al. replaces several + * of these routines with SMTC-specific variants. + */ +@@ -30,6 +46,7 @@ cnt = read_c0_count(); cnt += delta; write_c0_compare(cnt); + compare_change_hazard(); res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; - #ifdef CONFIG_MIPS_MT_SMTC - evpe(vpflags); -@@ -187,7 +204,7 @@ - */ - if (c0_compare_int_pending()) { - write_c0_compare(read_c0_count()); -- irq_disable_hazard(); -+ compare_change_hazard(); - if (c0_compare_int_pending()) - return 0; - } -@@ -196,7 +213,7 @@ - cnt = read_c0_count(); - cnt += delta; - write_c0_compare(cnt); -- irq_disable_hazard(); -+ compare_change_hazard(); - if ((int)(read_c0_count() - cnt) < 0) - break; - /* increase delta if the timer was already expired */ -@@ -205,11 +222,12 @@ - while ((int)(read_c0_count() - cnt) <= 0) - ; /* Wait for expiry */ - -+ compare_change_hazard(); - if (!c0_compare_int_pending()) - return 0; - - write_c0_compare(read_c0_count()); -- irq_disable_hazard(); -+ compare_change_hazard(); - if (c0_compare_int_pending()) - return 0; + return res; + } +@@ -99,22 +116,6 @@ + return (read_c0_cause() >> cp0_compare_irq) & 0x100; + } +-/* +- * Compare interrupt can be routed and latched outside the core, +- * so a single execution hazard barrier may not be enough to give +- * it time to clear as seen in the Cause register. 4 time the +- * pipeline depth seems reasonably conservative, and empirically +- * works better in configurations with high CPU/bus clock ratios. +- */ +- +-#define compare_change_hazard() \ +- do { \ +- irq_disable_hazard(); \ +- irq_disable_hazard(); \ +- irq_disable_hazard(); \ +- irq_disable_hazard(); \ +- } while (0) +- + int c0_compare_int_usable(void) + { + unsigned int delta; |