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| author | Gabor Juhos <juhosg@openwrt.org> | 2011-04-07 20:52:49 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2011-04-07 20:52:49 +0000 |
| commit | 91470edada63138ca56dc0b911e3827cfc348d81 (patch) | |
| tree | f3b53579579193891e5c2842ccac4a015e268ef4 /target | |
| parent | 3b209880bcf2ef55d69579ee81cadfc045cf4d4a (diff) | |
| download | master-31e0f0ae-91470edada63138ca56dc0b911e3827cfc348d81.tar.gz master-31e0f0ae-91470edada63138ca56dc0b911e3827cfc348d81.tar.bz2 master-31e0f0ae-91470edada63138ca56dc0b911e3827cfc348d81.zip | |
ar71xx: add AR934x specific glue for IRQ initialization
Signed-off-by: Jaiganesh Narayanan <jnarayanan@atheros.com>
SVN-Revision: 26510
Diffstat (limited to 'target')
3 files changed, 48 insertions, 5 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c index 08317b42cc..12919f7e58 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c @@ -1,10 +1,12 @@ /* * Atheros AR71xx SoC specific interrupt handling * + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> * - * Parts of this file are based on Atheros' 2.6.15 BSP + * Parts of this file are based on Atheros 2.6.15 BSP + * Parts of this file are based on Atheros 2.6.31 BSP * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published @@ -146,6 +148,21 @@ static void ar71xx_misc_irq_dispatch(void) else if (pending & MISC_INT_WDOG) do_IRQ(AR71XX_MISC_IRQ_WDOG); + else if (pending & MISC_INT_TIMER2) + do_IRQ(AR71XX_MISC_IRQ_TIMER2); + + else if (pending & MISC_INT_TIMER3) + do_IRQ(AR71XX_MISC_IRQ_TIMER3); + + else if (pending & MISC_INT_TIMER4) + do_IRQ(AR71XX_MISC_IRQ_TIMER4); + + else if (pending & MISC_INT_DDR_PERF) + do_IRQ(AR71XX_MISC_IRQ_DDR_PERF); + + else if (pending & MISC_INT_ENET_LINK) + do_IRQ(AR71XX_MISC_IRQ_ENET_LINK); + else spurious_interrupt(); } @@ -215,6 +232,9 @@ static void __init ar71xx_misc_irq_init(void) case AR71XX_SOC_AR7240: case AR71XX_SOC_AR7241: case AR71XX_SOC_AR7242: + case AR71XX_SOC_AR9341: + case AR71XX_SOC_AR9342: + case AR71XX_SOC_AR9344: ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack; break; default: @@ -281,10 +301,17 @@ void __init arch_init_irq(void) case AR71XX_SOC_AR9132: ip2_flush_reg = AR91XX_DDR_REG_FLUSH_WMAC; break; + case AR71XX_SOC_AR9341: + case AR71XX_SOC_AR9342: + case AR71XX_SOC_AR9344: + ip2_flush_reg = AR934X_DDR_REG_FLUSH_PCIE; + break; + default: ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI; break; } + mips_cpu_irq_init(); ar71xx_misc_irq_init(); diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h index 0a31678626..ab00d19e18 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @@ -75,10 +75,10 @@ #define AR71XX_CPU_IRQ_BASE 0 #define AR71XX_MISC_IRQ_BASE 8 -#define AR71XX_MISC_IRQ_COUNT 8 -#define AR71XX_GPIO_IRQ_BASE 16 +#define AR71XX_MISC_IRQ_COUNT 32 +#define AR71XX_GPIO_IRQ_BASE 40 #define AR71XX_GPIO_IRQ_COUNT 32 -#define AR71XX_PCI_IRQ_BASE 48 +#define AR71XX_PCI_IRQ_BASE 72 #define AR71XX_PCI_IRQ_COUNT 8 #define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2) @@ -96,6 +96,11 @@ #define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5) #define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6) #define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7) +#define AR71XX_MISC_IRQ_TIMER2 (AR71XX_MISC_IRQ_BASE + 8) +#define AR71XX_MISC_IRQ_TIMER3 (AR71XX_MISC_IRQ_BASE + 9) +#define AR71XX_MISC_IRQ_TIMER4 (AR71XX_MISC_IRQ_BASE + 10) +#define AR71XX_MISC_IRQ_DDR_PERF (AR71XX_MISC_IRQ_BASE + 11) +#define AR71XX_MISC_IRQ_ENET_LINK (AR71XX_MISC_IRQ_BASE + 12) #define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x)) @@ -465,6 +470,12 @@ void ar71xx_gpio_function_setup(u32 set, u32 clear); #define AR91XX_DDR_REG_FLUSH_USB 0x84 #define AR91XX_DDR_REG_FLUSH_WMAC 0x88 +#define AR934X_DDR_REG_FLUSH_GE0 0x9c +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 +#define AR934X_DDR_REG_FLUSH_USB 0xa4 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 + + #define PCI_WIN0_OFFS 0x10000000 #define PCI_WIN1_OFFS 0x11000000 #define PCI_WIN2_OFFS 0x12000000 @@ -564,6 +575,11 @@ void ar71xx_ddr_flush(u32 reg); #define WDOG_CTRL_ACTION_NMI 2 /* NMI */ #define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */ +#define MISC_INT_ENET_LINK BIT(12) +#define MISC_INT_DDR_PERF BIT(11) +#define MISC_INT_TIMER4 BIT(10) +#define MISC_INT_TIMER3 BIT(9) +#define MISC_INT_TIMER2 BIT(8) #define MISC_INT_DMA BIT(7) #define MISC_INT_OHCI BIT(6) #define MISC_INT_PERFC BIT(5) diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/irq.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/irq.h index 2197a10810..c61d9c73fd 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/irq.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/irq.h @@ -10,7 +10,7 @@ #define __ASM_MACH_AR71XX_IRQ_H #define MIPS_CPU_IRQ_BASE 0 -#define NR_IRQS 56 +#define NR_IRQS 80 #include_next <irq.h> |