diff options
| author | Felix Fietkau <nbd@openwrt.org> | 2010-03-28 00:35:44 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2010-03-28 00:35:44 +0000 |
| commit | 2cc215f1217e6d07283e9a26bec5c13f9cd2b9ba (patch) | |
| tree | 30364dafb51d92eac662393ca1e9fd5972732783 /target | |
| parent | 8701291f0f7f20c5d8d815f34ed8f5ae3ee1b888 (diff) | |
| download | master-31e0f0ae-2cc215f1217e6d07283e9a26bec5c13f9cd2b9ba.tar.gz master-31e0f0ae-2cc215f1217e6d07283e9a26bec5c13f9cd2b9ba.tar.bz2 master-31e0f0ae-2cc215f1217e6d07283e9a26bec5c13f9cd2b9ba.zip | |
ar71xx: reset the mdio bus on ar7241/ar7242
SVN-Revision: 20528
Diffstat (limited to 'target')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ar71xx/devices.c | 5 | ||||
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c b/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c index a7714eef9f..f809deae55 100644 --- a/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c +++ b/target/linux/ar71xx/files/arch/mips/ar71xx/devices.c @@ -436,9 +436,12 @@ void __init ar71xx_add_device_eth(unsigned int id) pdata->has_gbit = 1; break; - case AR71XX_SOC_AR7240: case AR71XX_SOC_AR7241: case AR71XX_SOC_AR7242: + ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO; + ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO; + /* fall through */ + case AR71XX_SOC_AR7240: pdata->ddr_flush = id ? ar724x_ddr_flush_ge1 : ar724x_ddr_flush_ge0; pdata->set_pll = id ? ar724x_set_pll_ge1 diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h index 7a7d75c3fe..c6a5a40995 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @@ -427,6 +427,8 @@ void ar71xx_ddr_flush(u32 reg); #define RESET_MODULE_PCI_BUS BIT(1) #define RESET_MODULE_PCI_CORE BIT(0) +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) #define AR724X_RESET_PCIE_PHY BIT(7) #define AR724X_RESET_PCIE BIT(6) |