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author | Gabor Juhos <juhosg@openwrt.org> | 2012-02-21 09:26:43 +0000 |
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committer | Gabor Juhos <juhosg@openwrt.org> | 2012-02-21 09:26:43 +0000 |
commit | 3ba0f4e1ca40c276117e1cacb27514d171f57812 (patch) | |
tree | 543ef67ed29ad86f38d987bb1ee73cb9426bcac0 /target/linux/ramips/files/drivers/net/ethernet | |
parent | a6d904b1d61b0985a3d4e2c323f8565382714330 (diff) | |
download | master-31e0f0ae-3ba0f4e1ca40c276117e1cacb27514d171f57812.tar.gz master-31e0f0ae-3ba0f4e1ca40c276117e1cacb27514d171f57812.tar.bz2 master-31e0f0ae-3ba0f4e1ca40c276117e1cacb27514d171f57812.zip |
ramips: move the ethernet driver into a separate directory
Also clean up the Kconfig symbols.
SVN-Revision: 30670
Diffstat (limited to 'target/linux/ramips/files/drivers/net/ethernet')
3 files changed, 1674 insertions, 0 deletions
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips.c b/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips.c new file mode 100644 index 0000000000..b9979fce5d --- /dev/null +++ b/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips.c @@ -0,0 +1,1025 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2009 John Crispin <blogic@openwrt.org> + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/dma-mapping.h> +#include <linux/init.h> +#include <linux/skbuff.h> +#include <linux/etherdevice.h> +#include <linux/ethtool.h> +#include <linux/platform_device.h> +#include <linux/phy.h> + +#include <ramips_eth_platform.h> +#include "ramips_eth.h" + +#define TX_TIMEOUT (20 * HZ / 100) +#define MAX_RX_LENGTH 1600 + +#ifdef CONFIG_RALINK_RT305X +#include "ramips_esw.c" +#else +static inline int rt305x_esw_init(void) { return 0; } +static inline void rt305x_esw_exit(void) { } +#endif + +#define phys_to_bus(a) (a & 0x1FFFFFFF) + +#ifdef CONFIG_RAMIPS_ETH_DEBUG +#define RADEBUG(fmt, args...) printk(KERN_DEBUG fmt, ## args) +#else +#define RADEBUG(fmt, args...) do {} while (0) +#endif + +static struct net_device * ramips_dev; +static void __iomem *ramips_fe_base = 0; + +static inline void +ramips_fe_wr(u32 val, unsigned reg) +{ + __raw_writel(val, ramips_fe_base + reg); +} + +static inline u32 +ramips_fe_rr(unsigned reg) +{ + return __raw_readl(ramips_fe_base + reg); +} + +static inline void +ramips_fe_int_disable(u32 mask) +{ + ramips_fe_wr(ramips_fe_rr(RAMIPS_FE_INT_ENABLE) & ~mask, + RAMIPS_FE_INT_ENABLE); + /* flush write */ + ramips_fe_rr(RAMIPS_FE_INT_ENABLE); +} + +static inline void +ramips_fe_int_enable(u32 mask) +{ + ramips_fe_wr(ramips_fe_rr(RAMIPS_FE_INT_ENABLE) | mask, + RAMIPS_FE_INT_ENABLE); + /* flush write */ + ramips_fe_rr(RAMIPS_FE_INT_ENABLE); +} + +static inline void +ramips_hw_set_macaddr(unsigned char *mac) +{ + ramips_fe_wr((mac[0] << 8) | mac[1], RAMIPS_GDMA1_MAC_ADRH); + ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], + RAMIPS_GDMA1_MAC_ADRL); +} + +static struct sk_buff * +ramips_alloc_skb(struct raeth_priv *re) +{ + struct sk_buff *skb; + + skb = netdev_alloc_skb(re->netdev, MAX_RX_LENGTH + NET_IP_ALIGN); + if (!skb) + return NULL; + + skb_reserve(skb, NET_IP_ALIGN); + + return skb; +} + +static void +ramips_ring_setup(struct raeth_priv *re) +{ + int len; + int i; + + len = NUM_TX_DESC * sizeof(struct ramips_tx_dma); + memset(re->tx, 0, len); + + for (i = 0; i < NUM_TX_DESC; i++) { + struct ramips_tx_dma *txd; + + txd = &re->tx[i]; + txd->txd4 = TX_DMA_QN(3) | TX_DMA_PN(1); + txd->txd2 = TX_DMA_LSO | TX_DMA_DONE; + + if (re->tx_skb[i] != NULL) { + netdev_warn(re->netdev, + "dirty skb for TX desc %d\n", i); + re->tx_skb[i] = NULL; + } + } + + len = NUM_RX_DESC * sizeof(struct ramips_rx_dma); + memset(re->rx, 0, len); + + for (i = 0; i < NUM_RX_DESC; i++) { + dma_addr_t dma_addr; + + BUG_ON(re->rx_skb[i] == NULL); + dma_addr = dma_map_single(&re->netdev->dev, re->rx_skb[i]->data, + MAX_RX_LENGTH, DMA_FROM_DEVICE); + re->rx_dma[i] = dma_addr; + re->rx[i].rxd1 = (unsigned int) dma_addr; + re->rx[i].rxd2 = RX_DMA_LSO; + } + + /* flush descriptors */ + wmb(); +} + +static void +ramips_ring_cleanup(struct raeth_priv *re) +{ + int i; + + for (i = 0; i < NUM_RX_DESC; i++) + if (re->rx_skb[i]) + dma_unmap_single(&re->netdev->dev, re->rx_dma[i], + MAX_RX_LENGTH, DMA_FROM_DEVICE); + + for (i = 0; i < NUM_TX_DESC; i++) + if (re->tx_skb[i]) { + dev_kfree_skb_any(re->tx_skb[i]); + re->tx_skb[i] = NULL; + } +} + +#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT3883) + +#define RAMIPS_MDIO_RETRY 1000 + +static unsigned char *ramips_speed_str(struct raeth_priv *re) +{ + switch (re->speed) { + case SPEED_1000: + return "1000"; + case SPEED_100: + return "100"; + case SPEED_10: + return "10"; + } + + return "?"; +} + +static void ramips_link_adjust(struct raeth_priv *re) +{ + struct ramips_eth_platform_data *pdata; + u32 mdio_cfg; + + pdata = re->parent->platform_data; + if (!re->link) { + netif_carrier_off(re->netdev); + netdev_info(re->netdev, "link down\n"); + return; + } + + mdio_cfg = RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 | + RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 | + RAMIPS_MDIO_CFG_GP1_FRC_EN; + + if (re->duplex == DUPLEX_FULL) + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_DUPLEX; + + if (re->tx_fc) + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_TX; + + if (re->rx_fc) + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_FC_RX; + + switch (re->speed) { + case SPEED_10: + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_10; + break; + case SPEED_100: + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_100; + break; + case SPEED_1000: + mdio_cfg |= RAMIPS_MDIO_CFG_GP1_SPEED_1000; + break; + default: + BUG(); + } + + ramips_fe_wr(mdio_cfg, RAMIPS_MDIO_CFG); + + netif_carrier_on(re->netdev); + netdev_info(re->netdev, "link up (%sMbps/%s duplex)\n", + ramips_speed_str(re), + (DUPLEX_FULL == re->duplex) ? "Full" : "Half"); +} + +static int +ramips_mdio_wait_ready(struct raeth_priv *re) +{ + int retries; + + retries = RAMIPS_MDIO_RETRY; + while (1) { + u32 t; + + t = ramips_fe_rr(RAMIPS_MDIO_ACCESS); + if ((t & (0x1 << 31)) == 0) + return 0; + + if (retries-- == 0) + break; + + udelay(1); + } + + dev_err(re->parent, "MDIO operation timed out\n"); + return -ETIMEDOUT; +} + +static int +ramips_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) +{ + struct raeth_priv *re = bus->priv; + int err; + u32 t; + + err = ramips_mdio_wait_ready(re); + if (err) + return 0xffff; + + t = (phy_addr << 24) | (phy_reg << 16); + ramips_fe_wr(t, RAMIPS_MDIO_ACCESS); + t |= (1 << 31); + ramips_fe_wr(t, RAMIPS_MDIO_ACCESS); + + err = ramips_mdio_wait_ready(re); + if (err) + return 0xffff; + + RADEBUG("%s: addr=%04x, reg=%04x, value=%04x\n", __func__, + phy_addr, phy_reg, ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff); + + return ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff; +} + +static int +ramips_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val) +{ + struct raeth_priv *re = bus->priv; + int err; + u32 t; + + RADEBUG("%s: addr=%04x, reg=%04x, value=%04x\n", __func__, + phy_addr, phy_reg, ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff); + + err = ramips_mdio_wait_ready(re); + if (err) + return err; + + t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val; + ramips_fe_wr(t, RAMIPS_MDIO_ACCESS); + t |= (1 << 31); + ramips_fe_wr(t, RAMIPS_MDIO_ACCESS); + + return ramips_mdio_wait_ready(re); +} + +static int +ramips_mdio_reset(struct mii_bus *bus) +{ + /* TODO */ + return 0; +} + +static int +ramips_mdio_init(struct raeth_priv *re) +{ + int err; + int i; + + re->mii_bus = mdiobus_alloc(); + if (re->mii_bus == NULL) + return -ENOMEM; + + re->mii_bus->name = "ramips_mdio"; + re->mii_bus->read = ramips_mdio_read; + re->mii_bus->write = ramips_mdio_write; + re->mii_bus->reset = ramips_mdio_reset; + re->mii_bus->irq = re->mii_irq; + re->mii_bus->priv = re; + re->mii_bus->parent = re->parent; + + snprintf(re->mii_bus->id, MII_BUS_ID_SIZE, "%s", "ramips_mdio"); + re->mii_bus->phy_mask = 0; + + for (i = 0; i < PHY_MAX_ADDR; i++) + re->mii_irq[i] = PHY_POLL; + + err = mdiobus_register(re->mii_bus); + if (err) + goto err_free_bus; + + return 0; + +err_free_bus: + kfree(re->mii_bus); + return err; +} + +static void +ramips_mdio_cleanup(struct raeth_priv *re) +{ + mdiobus_unregister(re->mii_bus); + kfree(re->mii_bus); +} + +static void +ramips_phy_link_adjust(struct net_device *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + struct phy_device *phydev = re->phy_dev; + unsigned long flags; + int status_change = 0; + + spin_lock_irqsave(&re->phy_lock, flags); + + if (phydev->link) + if (re->duplex != phydev->duplex || + re->speed != phydev->speed) + status_change = 1; + + if (phydev->link != re->link) + status_change = 1; + + re->link = phydev->link; + re->duplex = phydev->duplex; + re->speed = phydev->speed; + + if (status_change) + ramips_link_adjust(re); + + spin_unlock_irqrestore(&re->phy_lock, flags); +} + +static int +ramips_phy_connect_multi(struct raeth_priv *re) +{ + struct net_device *netdev = re->netdev; + struct ramips_eth_platform_data *pdata; + struct phy_device *phydev = NULL; + int phy_addr; + int ret = 0; + + pdata = re->parent->platform_data; + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { + if (!(pdata->phy_mask & (1 << phy_addr))) + continue; + + if (re->mii_bus->phy_map[phy_addr] == NULL) + continue; + + RADEBUG("%s: PHY found at %s, uid=%08x\n", + netdev->name, + dev_name(&re->mii_bus->phy_map[phy_addr]->dev), + re->mii_bus->phy_map[phy_addr]->phy_id); + + if (phydev == NULL) + phydev = re->mii_bus->phy_map[phy_addr]; + } + + if (!phydev) { + netdev_err(netdev, "no PHY found with phy_mask=%08x\n", + pdata->phy_mask); + return -ENODEV; + } + + re->phy_dev = phy_connect(netdev, dev_name(&phydev->dev), + ramips_phy_link_adjust, 0, + pdata->phy_if_mode); + + if (IS_ERR(re->phy_dev)) { + netdev_err(netdev, "could not connect to PHY at %s\n", + dev_name(&phydev->dev)); + return PTR_ERR(re->phy_dev); + } + + phydev->supported &= PHY_GBIT_FEATURES; + phydev->advertising = phydev->supported; + + RADEBUG("%s: connected to PHY at %s [uid=%08x, driver=%s]\n", + netdev->name, dev_name(&phydev->dev), + phydev->phy_id, phydev->drv->name); + + re->link = 0; + re->speed = 0; + re->duplex = -1; + re->rx_fc = 0; + re->tx_fc = 0; + + return ret; +} + +static int +ramips_phy_connect_fixed(struct raeth_priv *re) +{ + struct ramips_eth_platform_data *pdata; + + pdata = re->parent->platform_data; + switch (pdata->speed) { + case SPEED_10: + case SPEED_100: + case SPEED_1000: + break; + default: + netdev_err(re->netdev, "invalid speed specified\n"); + return -EINVAL; + } + + RADEBUG("%s: using fixed link parameters\n", re->netdev->name); + + re->speed = pdata->speed; + re->duplex = pdata->duplex; + re->tx_fc = pdata->tx_fc; + re->rx_fc = pdata->tx_fc; + + return 0; +} + +static int +ramips_phy_connect(struct raeth_priv *re) +{ + struct ramips_eth_platform_data *pdata; + + pdata = re->parent->platform_data; + if (pdata->phy_mask) + return ramips_phy_connect_multi(re); + + return ramips_phy_connect_fixed(re); +} + +static void +ramips_phy_disconnect(struct raeth_priv *re) +{ + if (re->phy_dev) + phy_disconnect(re->phy_dev); +} + +static void +ramips_phy_start(struct raeth_priv *re) +{ + unsigned long flags; + + if (re->phy_dev) { + phy_start(re->phy_dev); + } else { + spin_lock_irqsave(&re->phy_lock, flags); + re->link = 1; + ramips_link_adjust(re); + spin_unlock_irqrestore(&re->phy_lock, flags); + } +} + +static void +ramips_phy_stop(struct raeth_priv *re) +{ + unsigned long flags; + + if (re->phy_dev) + phy_stop(re->phy_dev); + + spin_lock_irqsave(&re->phy_lock, flags); + re->link = 0; + ramips_link_adjust(re); + spin_unlock_irqrestore(&re->phy_lock, flags); +} +#else +static inline int +ramips_mdio_init(struct raeth_priv *re) +{ + return 0; +} + +static inline void +ramips_mdio_cleanup(struct raeth_priv *re) +{ +} + +static inline int +ramips_phy_connect(struct raeth_priv *re) +{ + return 0; +} + +static inline void +ramips_phy_disconnect(struct raeth_priv *re) +{ +} + +static inline void +ramips_phy_start(struct raeth_priv *re) +{ +} + +static inline void +ramips_phy_stop(struct raeth_priv *re) +{ +} +#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT3883 */ + +static void +ramips_ring_free(struct raeth_priv *re) +{ + int len; + int i; + + for (i = 0; i < NUM_RX_DESC; i++) + if (re->rx_skb[i]) + dev_kfree_skb_any(re->rx_skb[i]); + + if (re->rx) { + len = NUM_RX_DESC * sizeof(struct ramips_rx_dma); + dma_free_coherent(&re->netdev->dev, len, re->rx, + re->rx_desc_dma); + } + + if (re->tx) { + len = NUM_TX_DESC * sizeof(struct ramips_tx_dma); + dma_free_coherent(&re->netdev->dev, len, re->tx, + re->tx_desc_dma); + } +} + +static int +ramips_ring_alloc(struct raeth_priv *re) +{ + int len; + int err = -ENOMEM; + int i; + + /* allocate tx ring */ + len = NUM_TX_DESC * sizeof(struct ramips_tx_dma); + re->tx = dma_alloc_coherent(&re->netdev->dev, len, + &re->tx_desc_dma, GFP_ATOMIC); + if (!re->tx) + goto err_cleanup; + + /* allocate rx ring */ + len = NUM_RX_DESC * sizeof(struct ramips_rx_dma); + re->rx = dma_alloc_coherent(&re->netdev->dev, len, + &re->rx_desc_dma, GFP_ATOMIC); + if (!re->rx) + goto err_cleanup; + + for (i = 0; i < NUM_RX_DESC; i++) { + struct sk_buff *skb; + + skb = ramips_alloc_skb(re); + if (!skb) + goto err_cleanup; + + re->rx_skb[i] = skb; + } + + return 0; + +err_cleanup: + ramips_ring_free(re); + return err; +} + +static void +ramips_setup_dma(struct raeth_priv *re) +{ + ramips_fe_wr(re->tx_desc_dma, RAMIPS_TX_BASE_PTR0); + ramips_fe_wr(NUM_TX_DESC, RAMIPS_TX_MAX_CNT0); + ramips_fe_wr(0, RAMIPS_TX_CTX_IDX0); + ramips_fe_wr(RAMIPS_PST_DTX_IDX0, RAMIPS_PDMA_RST_CFG); + + ramips_fe_wr(re->rx_desc_dma, RAMIPS_RX_BASE_PTR0); + ramips_fe_wr(NUM_RX_DESC, RAMIPS_RX_MAX_CNT0); + ramips_fe_wr((NUM_RX_DESC - 1), RAMIPS_RX_CALC_IDX0); + ramips_fe_wr(RAMIPS_PST_DRX_IDX0, RAMIPS_PDMA_RST_CFG); +} + +static int +ramips_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + unsigned long tx; + unsigned int tx_next; + dma_addr_t mapped_addr; + + if (re->plat->min_pkt_len) { + if (skb->len < re->plat->min_pkt_len) { + if (skb_padto(skb, re->plat->min_pkt_len)) { + printk(KERN_ERR + "ramips_eth: skb_padto failed\n"); + kfree_skb(skb); + return 0; + } + skb_put(skb, re->plat->min_pkt_len - skb->len); + } + } + + dev->trans_start = jiffies; + mapped_addr = dma_map_single(&re->netdev->dev, skb->data, skb->len, + DMA_TO_DEVICE); + + spin_lock(&re->page_lock); + tx = ramips_fe_rr(RAMIPS_TX_CTX_IDX0); + tx_next = (tx + 1) % NUM_TX_DESC; + + if ((re->tx_skb[tx]) || (re->tx_skb[tx_next]) || + !(re->tx[tx].txd2 & TX_DMA_DONE) || + !(re->tx[tx_next].txd2 & TX_DMA_DONE)) + goto out; + + re->tx[tx].txd1 = (unsigned int) mapped_addr; + re->tx[tx].txd2 &= ~(TX_DMA_PLEN0_MASK | TX_DMA_DONE); + re->tx[tx].txd2 |= TX_DMA_PLEN0(skb->len); + dev->stats.tx_packets++; + dev->stats.tx_bytes += skb->len; + re->tx_skb[tx] = skb; + wmb(); + ramips_fe_wr(tx_next, RAMIPS_TX_CTX_IDX0); + spin_unlock(&re->page_lock); + return NETDEV_TX_OK; + + out: + spin_unlock(&re->page_lock); + dev->stats.tx_dropped++; + kfree_skb(skb); + return NETDEV_TX_OK; +} + +static void +ramips_eth_rx_hw(unsigned long ptr) +{ + struct net_device *dev = (struct net_device *) ptr; + struct raeth_priv *re = netdev_priv(dev); + int rx; + int max_rx = 16; + + while (max_rx) { + struct sk_buff *rx_skb, *new_skb; + int pktlen; + + rx = (ramips_fe_rr(RAMIPS_RX_CALC_IDX0) + 1) % NUM_RX_DESC; + if (!(re->rx[rx].rxd2 & RX_DMA_DONE)) + break; + max_rx--; + + rx_skb = re->rx_skb[rx]; + pktlen = RX_DMA_PLEN0(re->rx[rx].rxd2); + + new_skb = ramips_alloc_skb(re); + /* Reuse the buffer on allocation failures */ + if (new_skb) { + dma_addr_t dma_addr; + + dma_unmap_single(&re->netdev->dev, re->rx_dma[rx], + MAX_RX_LENGTH, DMA_FROM_DEVICE); + + skb_put(rx_skb, pktlen); + rx_skb->dev = dev; + rx_skb->protocol = eth_type_trans(rx_skb, dev); + rx_skb->ip_summed = CHECKSUM_NONE; + dev->stats.rx_packets++; + dev->stats.rx_bytes += pktlen; + netif_rx(rx_skb); + + re->rx_skb[rx] = new_skb; + + dma_addr = dma_map_single(&re->netdev->dev, + new_skb->data, + MAX_RX_LENGTH, + DMA_FROM_DEVICE); + re->rx_dma[rx] = dma_addr; + re->rx[rx].rxd1 = (unsigned int) dma_addr; + } else { + dev->stats.rx_dropped++; + } + + re->rx[rx].rxd2 &= ~RX_DMA_DONE; + wmb(); + ramips_fe_wr(rx, RAMIPS_RX_CALC_IDX0); + } + + if (max_rx == 0) + tasklet_schedule(&re->rx_tasklet); + else + ramips_fe_int_enable(RAMIPS_RX_DLY_INT); +} + +static void +ramips_eth_tx_housekeeping(unsigned long ptr) +{ + struct net_device *dev = (struct net_device*)ptr; + struct raeth_priv *re = netdev_priv(dev); + + spin_lock(&re->page_lock); + while ((re->tx[re->skb_free_idx].txd2 & TX_DMA_DONE) && + (re->tx_skb[re->skb_free_idx])) { + dev_kfree_skb_irq(re->tx_skb[re->skb_free_idx]); + re->tx_skb[re->skb_free_idx] = 0; + re->skb_free_idx++; + if (re->skb_free_idx >= NUM_TX_DESC) + re->skb_free_idx = 0; + } + spin_unlock(&re->page_lock); + + ramips_fe_int_enable(RAMIPS_TX_DLY_INT); +} + +static void +ramips_eth_timeout(struct net_device *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + + tasklet_schedule(&re->tx_housekeeping_tasklet); +} + +static irqreturn_t +ramips_eth_irq(int irq, void *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + unsigned long fe_int = ramips_fe_rr(RAMIPS_FE_INT_STATUS); + + ramips_fe_wr(0xFFFFFFFF, RAMIPS_FE_INT_STATUS); + + if (fe_int & RAMIPS_RX_DLY_INT) { + ramips_fe_int_disable(RAMIPS_RX_DLY_INT); + tasklet_schedule(&re->rx_tasklet); + } + + if (fe_int & RAMIPS_TX_DLY_INT) { + ramips_fe_int_disable(RAMIPS_TX_DLY_INT); + tasklet_schedule(&re->tx_housekeeping_tasklet); + } + + return IRQ_HANDLED; +} + +static int +ramips_eth_open(struct net_device *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + int err; + + err = request_irq(dev->irq, ramips_eth_irq, IRQF_DISABLED, + dev->name, dev); + if (err) + return err; + + err = ramips_ring_alloc(re); + if (err) + goto err_free_irq; + + ramips_ring_setup(re); + ramips_hw_set_macaddr(dev->dev_addr); + + ramips_setup_dma(re); + ramips_fe_wr((ramips_fe_rr(RAMIPS_PDMA_GLO_CFG) & 0xff) | + (RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN | + RAMIPS_TX_DMA_EN | RAMIPS_PDMA_SIZE_4DWORDS), + RAMIPS_PDMA_GLO_CFG); + ramips_fe_wr((ramips_fe_rr(RAMIPS_FE_GLO_CFG) & + ~(RAMIPS_US_CYC_CNT_MASK << RAMIPS_US_CYC_CNT_SHIFT)) | + ((re->plat->sys_freq / RAMIPS_US_CYC_CNT_DIVISOR) << RAMIPS_US_CYC_CNT_SHIFT), + RAMIPS_FE_GLO_CFG); + + tasklet_init(&re->tx_housekeeping_tasklet, ramips_eth_tx_housekeeping, + (unsigned long)dev); + tasklet_init(&re->rx_tasklet, ramips_eth_rx_hw, (unsigned long)dev); + + ramips_phy_start(re); + + ramips_fe_wr(RAMIPS_DELAY_INIT, RAMIPS_DLY_INT_CFG); + ramips_fe_wr(RAMIPS_TX_DLY_INT | RAMIPS_RX_DLY_INT, RAMIPS_FE_INT_ENABLE); + ramips_fe_wr(ramips_fe_rr(RAMIPS_GDMA1_FWD_CFG) & + ~(RAMIPS_GDM1_ICS_EN | RAMIPS_GDM1_TCS_EN | RAMIPS_GDM1_UCS_EN | 0xffff), + RAMIPS_GDMA1_FWD_CFG); + ramips_fe_wr(ramips_fe_rr(RAMIPS_CDMA_CSG_CFG) & + ~(RAMIPS_ICS_GEN_EN | RAMIPS_TCS_GEN_EN | RAMIPS_UCS_GEN_EN), + RAMIPS_CDMA_CSG_CFG); + ramips_fe_wr(RAMIPS_PSE_FQFC_CFG_INIT, RAMIPS_PSE_FQ_CFG); + ramips_fe_wr(1, RAMIPS_FE_RST_GL); + ramips_fe_wr(0, RAMIPS_FE_RST_GL); + + netif_start_queue(dev); + return 0; + + err_free_irq: + free_irq(dev->irq, dev); + return err; +} + +static int +ramips_eth_stop(struct net_device *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + + ramips_fe_wr(ramips_fe_rr(RAMIPS_PDMA_GLO_CFG) & + ~(RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN | RAMIPS_TX_DMA_EN), + RAMIPS_PDMA_GLO_CFG); + + /* disable all interrupts in the hw */ + ramips_fe_wr(0, RAMIPS_FE_INT_ENABLE); + + ramips_phy_stop(re); + free_irq(dev->irq, dev); + netif_stop_queue(dev); + tasklet_kill(&re->tx_housekeeping_tasklet); + tasklet_kill(&re->rx_tasklet); + ramips_ring_cleanup(re); + ramips_ring_free(re); + RADEBUG("ramips_eth: stopped\n"); + return 0; +} + +static int __init +ramips_eth_probe(struct net_device *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + int err; + + BUG_ON(!re->plat->reset_fe); + re->plat->reset_fe(); + net_srandom(jiffies); + memcpy(dev->dev_addr, re->plat->mac, ETH_ALEN); + + ether_setup(dev); + dev->mtu = 1500; + dev->watchdog_timeo = TX_TIMEOUT; + spin_lock_init(&re->page_lock); + spin_lock_init(&re->phy_lock); + + err = ramips_mdio_init(re); + if (err) + return err; + + err = ramips_phy_connect(re); + if (err) + goto err_mdio_cleanup; + + return 0; + +err_mdio_cleanup: + ramips_mdio_cleanup(re); + return err; +} + +static void +ramips_eth_uninit(struct net_device *dev) +{ + struct raeth_priv *re = netdev_priv(dev); + + ramips_phy_disconnect(re); + ramips_mdio_cleanup(re); +} + +static const struct net_device_ops ramips_eth_netdev_ops = { + .ndo_init = ramips_eth_probe, + .ndo_uninit = ramips_eth_uninit, + .ndo_open = ramips_eth_open, + .ndo_stop = ramips_eth_stop, + .ndo_start_xmit = ramips_eth_hard_start_xmit, + .ndo_tx_timeout = ramips_eth_timeout, + .ndo_change_mtu = eth_change_mtu, + .ndo_set_mac_address = eth_mac_addr, + .ndo_validate_addr = eth_validate_addr, +}; + +static int +ramips_eth_plat_probe(struct platform_device *plat) +{ + struct raeth_priv *re; + struct ramips_eth_platform_data *data = plat->dev.platform_data; + struct resource *res; + int err; + + if (!data) { + dev_err(&plat->dev, "no platform data specified\n"); + return -EINVAL; + } + + res = platform_get_resource(plat, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&plat->dev, "no memory resource found\n"); + return -ENXIO; + } + + ramips_fe_base = ioremap_nocache(res->start, res->end - res->start + 1); + if (!ramips_fe_base) + return -ENOMEM; + + ramips_dev = alloc_etherdev(sizeof(struct raeth_priv)); + if (!ramips_dev) { + dev_err(&plat->dev, "alloc_etherdev failed\n"); + err = -ENOMEM; + goto err_unmap; + } + + strcpy(ramips_dev->name, "eth%d"); + ramips_dev->irq = platform_get_irq(plat, 0); + if (ramips_dev->irq < 0) { + dev_err(&plat->dev, "no IRQ resource found\n"); + err = -ENXIO; + goto err_free_dev; + } + ramips_dev->addr_len = ETH_ALEN; + ramips_dev->base_addr = (unsigned long)ramips_fe_base; + ramips_dev->netdev_ops = &ramips_eth_netdev_ops; + + re = netdev_priv(ramips_dev); + + re->netdev = ramips_dev; + re->parent = &plat->dev; + re->speed = data->speed; + re->duplex = data->duplex; + re->rx_fc = data->rx_fc; + re->tx_fc = data->tx_fc; + re->plat = data; + + err = register_netdev(ramips_dev); + if (err) { + dev_err(&plat->dev, "error bringing up device\n"); + goto err_free_dev; + } + + RADEBUG("ramips_eth: loaded\n"); + return 0; + + err_free_dev: + kfree(ramips_dev); + err_unmap: + iounmap(ramips_fe_base); + return err; +} + +static int +ramips_eth_plat_remove(struct platform_device *plat) +{ + unregister_netdev(ramips_dev); + free_netdev(ramips_dev); + RADEBUG("ramips_eth: unloaded\n"); + return 0; +} + +static struct platform_driver ramips_eth_driver = { + .probe = ramips_eth_plat_probe, + .remove = ramips_eth_plat_remove, + .driver = { + .name = "ramips_eth", + .owner = THIS_MODULE, + }, +}; + +static int __init +ramips_eth_init(void) +{ + int ret; + + ret = rt305x_esw_init(); + if (ret) + return ret; + + ret = platform_driver_register(&ramips_eth_driver); + if (ret) { + printk(KERN_ERR + "ramips_eth: Error registering platfom driver!\n"); + goto esw_cleanup; + } + + return 0; + +esw_cleanup: + rt305x_esw_exit(); + return ret; +} + +static void __exit +ramips_eth_cleanup(void) +{ + platform_driver_unregister(&ramips_eth_driver); + rt305x_esw_exit(); +} + +module_init(ramips_eth_init); +module_exit(ramips_eth_cleanup); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); +MODULE_DESCRIPTION("ethernet driver for ramips boards"); diff --git a/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_esw.c b/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_esw.c new file mode 100644 index 0000000000..a2fa579d8b --- /dev/null +++ b/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_esw.c @@ -0,0 +1,401 @@ +#include <linux/ioport.h> + +#include <rt305x_regs.h> +#include <rt305x_esw_platform.h> + +#define RT305X_ESW_REG_FCT0 0x08 +#define RT305X_ESW_REG_PFC1 0x14 +#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n)) +#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n)) +#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n)) +#define RT305X_ESW_REG_FPA 0x84 +#define RT305X_ESW_REG_SOCPC 0x8c +#define RT305X_ESW_REG_POC1 0x90 +#define RT305X_ESW_REG_POC2 0x94 +#define RT305X_ESW_REG_POC3 0x98 +#define RT305X_ESW_REG_SGC 0x9c +#define RT305X_ESW_REG_PCR0 0xc0 +#define RT305X_ESW_REG_PCR1 0xc4 +#define RT305X_ESW_REG_FPA2 0xc8 +#define RT305X_ESW_REG_FCT2 0xcc +#define RT305X_ESW_REG_SGC2 0xe4 +#define RT305X_ESW_REG_P0LED 0xa4 +#define RT305X_ESW_REG_P1LED 0xa8 +#define RT305X_ESW_REG_P2LED 0xac +#define RT305X_ESW_REG_P3LED 0xb0 +#define RT305X_ESW_REG_P4LED 0xb4 + +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16 +#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13) +#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8 + +#define RT305X_ESW_PCR1_WT_DONE BIT(0) + +#define RT305X_ESW_PHY_TIMEOUT (5 * HZ) + +#define RT305X_ESW_PVIDC_PVID_M 0xfff +#define RT305X_ESW_PVIDC_PVID_S 12 + +#define RT305X_ESW_VLANI_VID_M 0xfff +#define RT305X_ESW_VLANI_VID_S 12 + +#define RT305X_ESW_VMSC_MSC_M 0xff +#define RT305X_ESW_VMSC_MSC_S 8 + +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25) + +#define RT305X_ESW_POC1_EN_BP_S 0 +#define RT305X_ESW_POC1_EN_FC_S 8 +#define RT305X_ESW_POC1_DIS_RMC2CPU_S 16 +#define RT305X_ESW_POC1_DIS_PORT_S 23 + +#define RT305X_ESW_POC3_UNTAG_EN_S 0 +#define RT305X_ESW_POC3_ENAGING_S 8 +#define RT305X_ESW_POC3_DIS_UC_PAUSE_S 16 + +#define RT305X_ESW_PORT0 0 +#define RT305X_ESW_PORT1 1 +#define RT305X_ESW_PORT2 2 +#define RT305X_ESW_PORT3 3 +#define RT305X_ESW_PORT4 4 +#define RT305X_ESW_PORT5 5 +#define RT305X_ESW_PORT6 6 + +#define RT305X_ESW_PORTS_INTERNAL \ + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \ + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \ + BIT(RT305X_ESW_PORT4)) + +#define RT305X_ESW_PORTS_NOCPU \ + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5)) + +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6) + +#define RT305X_ESW_PORTS_ALL \ + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU) + +#define RT305X_ESW_NUM_VLANS 16 +#define RT305X_ESW_NUM_PORTS 7 + +struct rt305x_esw { + void __iomem *base; + struct rt305x_esw_platform_data *pdata; + spinlock_t reg_rw_lock; +}; + +static inline void +rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg) +{ + __raw_writel(val, esw->base + reg); +} + +static inline u32 +rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg) +{ + return __raw_readl(esw->base + reg); +} + +static inline void +rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask, + unsigned long val) +{ + unsigned long t; + + t = __raw_readl(esw->base + reg) & ~mask; + __raw_writel(t | val, esw->base + reg); +} + +static void +rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask, + unsigned long val) +{ + unsigned long flags; + + spin_lock_irqsave(&esw->reg_rw_lock, flags); + rt305x_esw_rmw_raw(esw, reg, mask, val); + spin_unlock_irqrestore(&esw->reg_rw_lock, flags); +} + +static u32 +rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register, + u32 write_data) +{ + unsigned long t_start = jiffies; + int ret = 0; + + while (1) { + if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) & + RT305X_ESW_PCR1_WT_DONE)) + break; + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) { + ret = 1; + goto out; + } + } + + write_data &= 0xffff; + rt305x_esw_wr(esw, + (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) | + (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) | + (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD, + RT305X_ESW_REG_PCR0); + + t_start = jiffies; + while (1) { + if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) & + RT305X_ESW_PCR1_WT_DONE) + break; + + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) { + ret = 1; + break; + } + } +out: + if (ret) + printk(KERN_ERR "ramips_eth: MDIO timeout\n"); + return ret; +} + +static void +rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid) +{ + unsigned s; + + s = RT305X_ESW_VLANI_VID_S * (vlan % 2); + rt305x_esw_rmw(esw, + RT305X_ESW_REG_VLANI(vlan / 2), + RT305X_ESW_VLANI_VID_M << s, + (vid & RT305X_ESW_VLANI_VID_M) << s); +} + +static void +rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid) +{ + unsigned s; + + s = RT305X_ESW_PVIDC_PVID_S * (port % 2); + rt305x_esw_rmw(esw, + RT305X_ESW_REG_PVIDC(port / 2), + RT305X_ESW_PVIDC_PVID_M << s, + (pvid & RT305X_ESW_PVIDC_PVID_M) << s); +} + +static void +rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc) +{ + unsigned s; + + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4); + rt305x_esw_rmw(esw, + RT305X_ESW_REG_VMSC(vlan / 4), + RT305X_ESW_VMSC_MSC_M << s, + (msc & RT305X_ESW_VMSC_MSC_M) << s); +} + +static void +rt305x_esw_hw_init(struct rt305x_esw *esw) +{ + int i; + + /* vodoo from original driver */ + rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0); + rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2); + rt305x_esw_wr(esw, 0x00405555, RT305X_ESW_REG_PFC1); + + /* Enable Back Pressure, and Flow Control */ + rt305x_esw_wr(esw, + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_BP_S) | + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_FC_S)), + RT305X_ESW_REG_POC1); + + /* Enable Aging, and VLAN TAG removal */ + rt305x_esw_wr(esw, + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC3_ENAGING_S) | + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC3_UNTAG_EN_S)), + RT305X_ESW_REG_POC3); + + rt305x_esw_wr(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2); + rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC); + + /* Setup SoC Port control register */ + rt305x_esw_wr(esw, + (RT305X_ESW_SOCPC_CRC_PADDING | + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) | + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) | + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)), + RT305X_ESW_REG_SOCPC); + + rt305x_esw_wr(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2); + rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA); + + /* Force Link/Activity on ports */ + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P0LED); + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P1LED); + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P2LED); + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P3LED); + rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P4LED); + + rt305x_mii_write(esw, 0, 31, 0x8000); + for (i = 0; i < 5; i++) { + /* TX10 waveform coefficient */ + rt305x_mii_write(esw, i, 0, 0x3100); + /* TX10 waveform coefficient */ + rt305x_mii_write(esw, i, 26, 0x1601); + /* TX100/TX10 AD/DA current bias */ + rt305x_mii_write(esw, i, 29, 0x7058); + /* TX100 slew rate control */ + rt305x_mii_write(esw, i, 30, 0x0018); + } + + /* PHY IOT */ + /* select global register */ + rt305x_mii_write(esw, 0, 31, 0x0); + /* tune TP_IDL tail and head waveform */ + rt305x_mii_write(esw, 0, 22, 0x052f); + /* set TX10 signal amplitude threshold to minimum */ + rt305x_mii_write(esw, 0, 17, 0x0fe0); + /* set squelch amplitude to higher threshold */ + rt305x_mii_write(esw, 0, 18, 0x40ba); + /* longer TP_IDL tail length */ + rt305x_mii_write(esw, 0, 14, 0x65); + /* select local register */ + rt305x_mii_write(esw, 0, 31, 0x8000); + + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) { + rt305x_esw_set_vlan_id(esw, i, 0); + rt305x_esw_set_vmsc(esw, i, 0); + } + + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) + rt305x_esw_set_pvid(esw, i, 1); + + switch (esw->pdata->vlan_config) { + case RT305X_ESW_VLAN_CONFIG_NONE: + break; + + case RT305X_ESW_VLAN_CONFIG_BYPASS: + /* Pass all vlan tags to all ports */ + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) { + rt305x_esw_set_vlan_id(esw, i, i+1); + rt305x_esw_set_vmsc(esw, i, RT305X_ESW_PORTS_ALL); + } + /* Disable VLAN TAG removal, keep aging on. */ + rt305x_esw_wr(esw, + RT305X_ESW_PORTS_ALL << RT305X_ESW_POC3_ENAGING_S, + RT305X_ESW_REG_POC3); + break; + + case RT305X_ESW_VLAN_CONFIG_LLLLW: + rt305x_esw_set_vlan_id(esw, 0, 1); + rt305x_esw_set_vlan_id(esw, 1, 2); + rt305x_esw_set_pvid(esw, RT305X_ESW_PORT4, 2); + + rt305x_esw_set_vmsc(esw, 0, + BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | + BIT(RT305X_ESW_PORT6)); + rt305x_esw_set_vmsc(esw, 1, + BIT(RT305X_ESW_PORT4) | BIT(RT305X_ESW_PORT6)); + break; + + case RT305X_ESW_VLAN_CONFIG_WLLLL: + rt305x_esw_set_vlan_id(esw, 0, 1); + rt305x_esw_set_vlan_id(esw, 1, 2); + rt305x_esw_set_pvid(esw, RT305X_ESW_PORT0, 2); + + rt305x_esw_set_vmsc(esw, 0, + BIT(RT305X_ESW_PORT1) | BIT(RT305X_ESW_PORT2) | + BIT(RT305X_ESW_PORT3) | BIT(RT305X_ESW_PORT4) | + BIT(RT305X_ESW_PORT6)); + rt305x_esw_set_vmsc(esw, 1, + BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT6)); + break; + + default: + BUG(); + } +} + +static int +rt305x_esw_probe(struct platform_device *pdev) +{ + struct rt305x_esw_platform_data *pdata; + struct rt305x_esw *esw; + struct resource *res; + int err; + + pdata = pdev->dev.platform_data; + if (!pdata) + return -EINVAL; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "no memory resource found\n"); + return -ENOMEM; + } + + esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL); + if (!esw) { + dev_err(&pdev->dev, "no memory for private data\n"); + return -ENOMEM; + } + + esw->base = ioremap(res->start, resource_size(res)); + if (!esw->base) { + dev_err(&pdev->dev, "ioremap failed\n"); + err = -ENOMEM; + goto free_esw; + } + + platform_set_drvdata(pdev, esw); + + esw->pdata = pdata; + spin_lock_init(&esw->reg_rw_lock); + rt305x_esw_hw_init(esw); + + return 0; + +free_esw: + kfree(esw); + return err; +} + +static int +rt305x_esw_remove(struct platform_device *pdev) +{ + struct rt305x_esw *esw; + + esw = platform_get_drvdata(pdev); + if (esw) { + platform_set_drvdata(pdev, NULL); + iounmap(esw->base); + kfree(esw); + } + + return 0; +} + +static struct platform_driver rt305x_esw_driver = { + .probe = rt305x_esw_probe, + .remove = rt305x_esw_remove, + .driver = { + .name = "rt305x-esw", + .owner = THIS_MODULE, + }, +}; + +static int __init +rt305x_esw_init(void) +{ + return platform_driver_register(&rt305x_esw_driver); +} + +static void +rt305x_esw_exit(void) +{ + platform_driver_unregister(&rt305x_esw_driver); +} diff --git a/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_eth.h b/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_eth.h new file mode 100644 index 0000000000..1d151df687 --- /dev/null +++ b/target/linux/ramips/files/drivers/net/ethernet/ramips/ramips_eth.h @@ -0,0 +1,248 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * based on Ralink SDK3.3 + * Copyright (C) 2009 John Crispin <blogic@openwrt.org> + */ + +#ifndef RAMIPS_ETH_H +#define RAMIPS_ETH_H + +#include <linux/mii.h> +#include <linux/interrupt.h> +#include <linux/netdevice.h> +#include <linux/dma-mapping.h> + +#define NUM_RX_DESC 256 +#define NUM_TX_DESC 256 + +#define RAMIPS_DELAY_EN_INT 0x80 +#define RAMIPS_DELAY_MAX_INT 0x04 +#define RAMIPS_DELAY_MAX_TOUT 0x04 +#define RAMIPS_DELAY_CHAN (((RAMIPS_DELAY_EN_INT | RAMIPS_DELAY_MAX_INT) << 8) | RAMIPS_DELAY_MAX_TOUT) +#define RAMIPS_DELAY_INIT ((RAMIPS_DELAY_CHAN << 16) | RAMIPS_DELAY_CHAN) +#define RAMIPS_PSE_FQFC_CFG_INIT 0x80504000 + +/* interrupt bits */ +#define RAMIPS_CNT_PPE_AF BIT(31) +#define RAMIPS_CNT_GDM_AF BIT(29) +#define RAMIPS_PSE_P2_FC BIT(26) +#define RAMIPS_PSE_BUF_DROP BIT(24) +#define RAMIPS_GDM_OTHER_DROP BIT(23) +#define RAMIPS_PSE_P1_FC BIT(22) +#define RAMIPS_PSE_P0_FC BIT(21) +#define RAMIPS_PSE_FQ_EMPTY BIT(20) +#define RAMIPS_GE1_STA_CHG BIT(18) +#define RAMIPS_TX_COHERENT BIT(17) +#define RAMIPS_RX_COHERENT BIT(16) +#define RAMIPS_TX_DONE_INT3 BIT(11) +#define RAMIPS_TX_DONE_INT2 BIT(10) +#define RAMIPS_TX_DONE_INT1 BIT(9) +#define RAMIPS_TX_DONE_INT0 BIT(8) +#define RAMIPS_RX_DONE_INT0 BIT(2) +#define RAMIPS_TX_DLY_INT BIT(1) +#define RAMIPS_RX_DLY_INT BIT(0) + +/* registers */ +#define RAMIPS_FE_OFFSET 0x0000 +#define RAMIPS_GDMA_OFFSET 0x0020 +#define RAMIPS_PSE_OFFSET 0x0040 +#define RAMIPS_GDMA2_OFFSET 0x0060 +#define RAMIPS_CDMA_OFFSET 0x0080 +#define RAMIPS_PDMA_OFFSET 0x0100 +#define RAMIPS_PPE_OFFSET 0x0200 +#define RAMIPS_CMTABLE_OFFSET 0x0400 +#define RAMIPS_POLICYTABLE_OFFSET 0x1000 + +#define RAMIPS_MDIO_ACCESS (RAMIPS_FE_OFFSET + 0x00) +#define RAMIPS_MDIO_CFG (RAMIPS_FE_OFFSET + 0x04) +#define RAMIPS_FE_GLO_CFG (RAMIPS_FE_OFFSET + 0x08) +#define RAMIPS_FE_RST_GL (RAMIPS_FE_OFFSET + 0x0C) +#define RAMIPS_FE_INT_STATUS (RAMIPS_FE_OFFSET + 0x10) +#define RAMIPS_FE_INT_ENABLE (RAMIPS_FE_OFFSET + 0x14) +#define RAMIPS_MDIO_CFG2 (RAMIPS_FE_OFFSET + 0x18) +#define RAMIPS_FOC_TS_T (RAMIPS_FE_OFFSET + 0x1C) + +#define RAMIPS_GDMA1_FWD_CFG (RAMIPS_GDMA_OFFSET + 0x00) +#define RAMIPS_GDMA1_SCH_CFG (RAMIPS_GDMA_OFFSET + 0x04) +#define RAMIPS_GDMA1_SHPR_CFG (RAMIPS_GDMA_OFFSET + 0x08) +#define RAMIPS_GDMA1_MAC_ADRL (RAMIPS_GDMA_OFFSET + 0x0C) +#define RAMIPS_GDMA1_MAC_ADRH (RAMIPS_GDMA_OFFSET + 0x10) + +#define RAMIPS_GDMA2_FWD_CFG (RAMIPS_GDMA2_OFFSET + 0x00) +#define RAMIPS_GDMA2_SCH_CFG (RAMIPS_GDMA2_OFFSET + 0x04) +#define RAMIPS_GDMA2_SHPR_CFG (RAMIPS_GDMA2_OFFSET + 0x08) +#define RAMIPS_GDMA2_MAC_ADRL (RAMIPS_GDMA2_OFFSET + 0x0C) +#define RAMIPS_GDMA2_MAC_ADRH (RAMIPS_GDMA2_OFFSET + 0x10) + +#define RAMIPS_PSE_FQ_CFG (RAMIPS_PSE_OFFSET + 0x00) +#define RAMIPS_CDMA_FC_CFG (RAMIPS_PSE_OFFSET + 0x04) +#define RAMIPS_GDMA1_FC_CFG (RAMIPS_PSE_OFFSET + 0x08) +#define RAMIPS_GDMA2_FC_CFG (RAMIPS_PSE_OFFSET + 0x0C) + +#define RAMIPS_CDMA_CSG_CFG (RAMIPS_CDMA_OFFSET + 0x00) +#define RAMIPS_CDMA_SCH_CFG (RAMIPS_CDMA_OFFSET + 0x04) + +#define RAMIPS_PDMA_GLO_CFG (RAMIPS_PDMA_OFFSET + 0x00) +#define RAMIPS_PDMA_RST_CFG (RAMIPS_PDMA_OFFSET + 0x04) +#define RAMIPS_PDMA_SCH_CFG (RAMIPS_PDMA_OFFSET + 0x08) +#define RAMIPS_DLY_INT_CFG (RAMIPS_PDMA_OFFSET + 0x0C) +#define RAMIPS_TX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x10) +#define RAMIPS_TX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x14) +#define RAMIPS_TX_CTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x18) +#define RAMIPS_TX_DTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x1C) +#define RAMIPS_TX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x20) +#define RAMIPS_TX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x24) +#define RAMIPS_TX_CTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x28) +#define RAMIPS_TX_DTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x2C) +#define RAMIPS_RX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x30) +#define RAMIPS_RX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x34) +#define RAMIPS_RX_CALC_IDX0 (RAMIPS_PDMA_OFFSET + 0x38) +#define RAMIPS_RX_DRX_IDX0 (RAMIPS_PDMA_OFFSET + 0x3C) +#define RAMIPS_TX_BASE_PTR2 (RAMIPS_PDMA_OFFSET + 0x40) +#define RAMIPS_TX_MAX_CNT2 (RAMIPS_PDMA_OFFSET + 0x44) +#define RAMIPS_TX_CTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x48) +#define RAMIPS_TX_DTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x4C) +#define RAMIPS_TX_BASE_PTR3 (RAMIPS_PDMA_OFFSET + 0x50) +#define RAMIPS_TX_MAX_CNT3 (RAMIPS_PDMA_OFFSET + 0x54) +#define RAMIPS_TX_CTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x58) +#define RAMIPS_TX_DTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x5C) +#define RAMIPS_RX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x60) +#define RAMIPS_RX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x64) +#define RAMIPS_RX_CALC_IDX1 (RAMIPS_PDMA_OFFSET + 0x68) +#define RAMIPS_RX_DRX_IDX1 (RAMIPS_PDMA_OFFSET + 0x6C) + +/* MDIO_CFG register bits */ +#define RAMIPS_MDIO_CFG_AUTO_POLL_EN BIT(29) +#define RAMIPS_MDIO_CFG_GP1_BP_EN BIT(16) +#define RAMIPS_MDIO_CFG_GP1_FRC_EN BIT(15) +#define RAMIPS_MDIO_CFG_GP1_SPEED_10 (0 << 13) +#define RAMIPS_MDIO_CFG_GP1_SPEED_100 (1 << 13) +#define RAMIPS_MDIO_CFG_GP1_SPEED_1000 (2 << 13) +#define RAMIPS_MDIO_CFG_GP1_DUPLEX BIT(12) +#define RAMIPS_MDIO_CFG_GP1_FC_TX BIT(11) +#define RAMIPS_MDIO_CFG_GP1_FC_RX BIT(10) +#define RAMIPS_MDIO_CFG_GP1_LNK_DWN BIT(9) +#define RAMIPS_MDIO_CFG_GP1_AN_FAIL BIT(8) +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6) +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6) +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6) +#define RAMIPS_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6) +#define RAMIPS_MDIO_CFG_TURBO_MII_FREQ BIT(5) +#define RAMIPS_MDIO_CFG_TURBO_MII_MODE BIT(4) +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2) +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2) +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2) +#define RAMIPS_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2) +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_0 0 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_200 1 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_400 2 +#define RAMIPS_MDIO_CFG_TX_CLK_SKEW_INV 3 + +/* uni-cast port */ +#define RAMIPS_GDM1_ICS_EN BIT(22) +#define RAMIPS_GDM1_TCS_EN BIT(21) +#define RAMIPS_GDM1_UCS_EN BIT(20) +#define RAMIPS_GDM1_JMB_EN BIT(19) +#define RAMIPS_GDM1_STRPCRC BIT(16) +#define RAMIPS_GDM1_UFRC_P_CPU (0 << 12) +#define RAMIPS_GDM1_UFRC_P_GDMA1 (1 << 12) +#define RAMIPS_GDM1_UFRC_P_PPE (6 << 12) + +/* checksums */ +#define RAMIPS_ICS_GEN_EN BIT(2) +#define RAMIPS_UCS_GEN_EN BIT(1) +#define RAMIPS_TCS_GEN_EN BIT(0) + +/* dma ring */ +#define RAMIPS_PST_DRX_IDX0 BIT(16) +#define RAMIPS_PST_DTX_IDX3 BIT(3) +#define RAMIPS_PST_DTX_IDX2 BIT(2) +#define RAMIPS_PST_DTX_IDX1 BIT(1) +#define RAMIPS_PST_DTX_IDX0 BIT(0) + +#define RAMIPS_TX_WB_DDONE BIT(6) +#define RAMIPS_RX_DMA_BUSY BIT(3) +#define RAMIPS_TX_DMA_BUSY BIT(1) +#define RAMIPS_RX_DMA_EN BIT(2) +#define RAMIPS_TX_DMA_EN BIT(0) + +#define RAMIPS_PDMA_SIZE_4DWORDS (0 << 4) +#define RAMIPS_PDMA_SIZE_8DWORDS (1 << 4) +#define RAMIPS_PDMA_SIZE_16DWORDS (2 << 4) + +#define RAMIPS_US_CYC_CNT_MASK 0xff +#define RAMIPS_US_CYC_CNT_SHIFT 0x8 +#define RAMIPS_US_CYC_CNT_DIVISOR 1000000 + +#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff) +#define RX_DMA_LSO BIT(30) +#define RX_DMA_DONE BIT(31) + +struct ramips_rx_dma { + unsigned int rxd1; + unsigned int rxd2; + unsigned int rxd3; + unsigned int rxd4; +} __packed __aligned(4); + +#define TX_DMA_PLEN0_MASK ((0x3fff) << 16) +#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) +#define TX_DMA_LSO BIT(30) +#define TX_DMA_DONE BIT(31) +#define TX_DMA_QN(_x) ((_x) << 16) +#define TX_DMA_PN(_x) ((_x) << 24) +#define TX_DMA_QN_MASK TX_DMA_QN(0x7) +#define TX_DMA_PN_MASK TX_DMA_PN(0x7) + +struct ramips_tx_dma { + unsigned int txd1; + unsigned int txd2; + unsigned int txd3; + unsigned int txd4; +} __packed __aligned(4); + +struct raeth_priv +{ + dma_addr_t rx_desc_dma; + struct tasklet_struct rx_tasklet; + struct ramips_rx_dma *rx; + struct sk_buff *rx_skb[NUM_RX_DESC]; + dma_addr_t rx_dma[NUM_RX_DESC]; + + dma_addr_t tx_desc_dma; + struct tasklet_struct tx_housekeeping_tasklet; + struct ramips_tx_dma *tx; + struct sk_buff *tx_skb[NUM_TX_DESC]; + + unsigned int skb_free_idx; + + spinlock_t page_lock; + struct net_device *netdev; + struct device *parent; + struct ramips_eth_platform_data *plat; + + int link; + int speed; + int duplex; + int tx_fc; + int rx_fc; + + struct mii_bus *mii_bus; + int mii_irq[PHY_MAX_ADDR]; + struct phy_device *phy_dev; + spinlock_t phy_lock; +}; + +#endif /* RAMIPS_ETH_H */ |