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| author | John Crispin <john@openwrt.org> | 2015-02-09 19:34:49 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2015-02-09 19:34:49 +0000 |
| commit | 07352ca2c725377b46e316e47b2bb4cb411b8135 (patch) | |
| tree | 6b3f2bfff672c19a74ee5dd9a865cb32e85ae8f1 /target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c | |
| parent | 525cd8aedb33d26a8f38e6b553e8d83a47d73bcc (diff) | |
| download | master-31e0f0ae-07352ca2c725377b46e316e47b2bb4cb411b8135.tar.gz master-31e0f0ae-07352ca2c725377b46e316e47b2bb4cb411b8135.tar.bz2 master-31e0f0ae-07352ca2c725377b46e316e47b2bb4cb411b8135.zip | |
ralink: fix hw status almost full not work on mt7620 and mt7621
the old FE_INT_STATUS register becomes two registers.
FE_INT_STATUS and INT_STATUS. so the hw status almost full
must change to read from FE_INT_STATUS register.
tx/rx done read from INT_STATUS register.
mt7620 datasheet define CNT_GDM1_AF at BIT(29).
but after test it should be BIT(13). why?
Signed-off-by: michael lee <igvtee@gmail.com>
SVN-Revision: 44371
Diffstat (limited to 'target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c')
| -rw-r--r-- | target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c index 6e2fbdf645..3d610ec38a 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c @@ -62,6 +62,15 @@ #define GSW_REG_GDMA1_MAC_ADRH 0x50C #define MT7621_FE_RST_GL (FE_FE_OFFSET + 0x04) +#define MT7620_FE_INT_STATUS2 (FE_FE_OFFSET + 0x08) + +/* + * FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29) + * but after test it should be BIT(13). + */ +#define MT7620_FE_GDM1_AF BIT(13) +#define MT7621_FE_GDM1_AF BIT(28) +#define MT7621_FE_GDM2_AF BIT(29) static const u32 mt7620_reg_table[FE_REG_COUNT] = { [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG, @@ -80,6 +89,7 @@ static const u32 mt7620_reg_table[FE_REG_COUNT] = { [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID, [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT, [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL, + [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2, }; static const u32 mt7621_reg_table[FE_REG_COUNT] = { @@ -99,6 +109,7 @@ static const u32 mt7621_reg_table[FE_REG_COUNT] = { [FE_REG_FE_DMA_VID_BASE] = 0, [FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT, [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL, + [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2, }; static void mt7620_fe_reset(void) @@ -231,6 +242,7 @@ static struct fe_soc_data mt7620_data = { .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS, .rx_int = RT5350_RX_DONE_INT, .tx_int = RT5350_TX_DONE_INT, + .status_int = MT7620_FE_GDM1_AF, .checksum_bit = MT7620_L4_VALID, .has_carrier = mt7620a_has_carrier, .mdio_read = mt7620_mdio_read, @@ -251,6 +263,7 @@ static struct fe_soc_data mt7621_data = { .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS, .rx_int = RT5350_RX_DONE_INT, .tx_int = RT5350_TX_DONE_INT, + .status_int = (MT7621_FE_GDM1_AF | MT7621_FE_GDM2_AF), .checksum_bit = MT7621_L4_VALID, .has_carrier = mt7620a_has_carrier, .mdio_read = mt7620_mdio_read, |