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| author | John Crispin <john@openwrt.org> | 2015-08-17 05:57:18 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2015-08-17 05:57:18 +0000 |
| commit | 553fea9f195aaefa8533b99e0d0c9ff9a27fc4f5 (patch) | |
| tree | aab9bba631d4ce922778932cff73412dffd67a5b /target/linux/ramips/dts/mt7620n.dtsi | |
| parent | cae35b268cc8db7186cf026543a3d89c2f2de028 (diff) | |
| download | master-31e0f0ae-553fea9f195aaefa8533b99e0d0c9ff9a27fc4f5.tar.gz master-31e0f0ae-553fea9f195aaefa8533b99e0d0c9ff9a27fc4f5.tar.bz2 master-31e0f0ae-553fea9f195aaefa8533b99e0d0c9ff9a27fc4f5.zip | |
ramips: fix indentation and other mistakes in .dts{, i} files
The following patch fixes:
* wrong indentations
* doubled gpio-keys-polled nodes (DIR-300-B7, DIR-320-B1, DIR-610-A1)
* duplicate spacings
* empty lines at end of files and after last child nodes
* trailing and leading whitespace
* unnecessary and commented-out code
* missing empty lines between nodes and between properties and nodes
* unnecessary empty lines between nodes properties [1]
in .dts{,i} files, for ramips target.
[1] Some of empty lines in SOCs dtsi files were left untouched, because they seem to be there for a reason (readability?).
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
SVN-Revision: 46613
Diffstat (limited to 'target/linux/ramips/dts/mt7620n.dtsi')
| -rw-r--r-- | target/linux/ramips/dts/mt7620n.dtsi | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/linux/ramips/dts/mt7620n.dtsi b/target/linux/ramips/dts/mt7620n.dtsi index 83ab03ae5d..e886c6fbec 100644 --- a/target/linux/ramips/dts/mt7620n.dtsi +++ b/target/linux/ramips/dts/mt7620n.dtsi @@ -23,7 +23,7 @@ palmbus@10000000 { compatible = "palmbus"; reg = <0x10000000 0x200000>; - ranges = <0x0 0x10000000 0x1FFFFF>; + ranges = <0x0 0x10000000 0x1FFFFF>; #address-cells = <1>; #size-cells = <1>; @@ -202,14 +202,17 @@ compatible = "ralink,rt2880-pinmux"; pinctrl-names = "default"; pinctrl-0 = <&state_default>; + state_default: pinctrl0 { }; + spi_pins: spi { spi { ralink,group = "spi"; ralink,function = "spi"; }; }; + uartlite_pins: uartlite { uart { ralink,group = "uartlite"; |