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| author | John Crispin <john@openwrt.org> | 2013-03-14 18:42:29 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2013-03-14 18:42:29 +0000 |
| commit | b98ae2b149e8eef38d3285d8e1b21af32ac1f2dc (patch) | |
| tree | 942791530060eeebfd3e6cd68158c74b892ed7ec /target/linux/lantiq/patches-3.8/0020-MIPS-lantiq-adds-4dword-burst-length-for-dma.patch | |
| parent | 3ab75692f3a7490146eaec4a5a76dec327f11f97 (diff) | |
| download | master-31e0f0ae-b98ae2b149e8eef38d3285d8e1b21af32ac1f2dc.tar.gz master-31e0f0ae-b98ae2b149e8eef38d3285d8e1b21af32ac1f2dc.tar.bz2 master-31e0f0ae-b98ae2b149e8eef38d3285d8e1b21af32ac1f2dc.zip | |
bump to v3.8
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 36014
Diffstat (limited to 'target/linux/lantiq/patches-3.8/0020-MIPS-lantiq-adds-4dword-burst-length-for-dma.patch')
| -rw-r--r-- | target/linux/lantiq/patches-3.8/0020-MIPS-lantiq-adds-4dword-burst-length-for-dma.patch | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-3.8/0020-MIPS-lantiq-adds-4dword-burst-length-for-dma.patch b/target/linux/lantiq/patches-3.8/0020-MIPS-lantiq-adds-4dword-burst-length-for-dma.patch new file mode 100644 index 0000000000..febc16aa78 --- /dev/null +++ b/target/linux/lantiq/patches-3.8/0020-MIPS-lantiq-adds-4dword-burst-length-for-dma.patch @@ -0,0 +1,34 @@ +From 5be3837d01ea56e1455781f1b51764bd896973f2 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Thu, 6 Dec 2012 11:59:23 +0100 +Subject: [PATCH 20/40] MIPS: lantiq: adds 4dword burst length for dma + +--- + arch/mips/lantiq/xway/dma.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c +index e44a186..c7684c9 100644 +--- a/arch/mips/lantiq/xway/dma.c ++++ b/arch/mips/lantiq/xway/dma.c +@@ -47,6 +47,7 @@ + #define DMA_IRQ_ACK 0x7e /* IRQ status register */ + #define DMA_POLL BIT(31) /* turn on channel polling */ + #define DMA_CLK_DIV4 BIT(6) /* polling clock divider */ ++#define DMA_4W_BURST BIT(2) /* 4 word burst length */ + #define DMA_2W_BURST BIT(1) /* 2 word burst length */ + #define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */ + #define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */ +@@ -195,7 +196,8 @@ ltq_dma_init_port(int p) + * Tell the DMA engine to swap the endianness of data frames and + * drop packets if the channel arbitration fails. + */ +- ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN, ++ ltq_dma_w32_mask(0, (DMA_4W_BURST << 4) | (DMA_4W_BURST << 2) | ++ DMA_ETOP_ENDIANNESS | DMA_PDEN, + LTQ_DMA_PCTRL); + break; + +-- +1.7.10.4 + |