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| author | John Crispin <john@openwrt.org> | 2015-10-19 10:08:18 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2015-10-19 10:08:18 +0000 |
| commit | 2c7d536780600242d804bca1383c896ccff350c4 (patch) | |
| tree | 014c507ad85917e83ea22f3f36fe136cc8e0ebf9 /target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch | |
| parent | 42c9a85e8e81cead3188481d8ff571e2a326e46b (diff) | |
| download | master-31e0f0ae-2c7d536780600242d804bca1383c896ccff350c4.tar.gz master-31e0f0ae-2c7d536780600242d804bca1383c896ccff350c4.tar.bz2 master-31e0f0ae-2c7d536780600242d804bca1383c896ccff350c4.zip | |
lantiq: Fixed reading the number of RX FIFOs in the SPI driver
Until now the SPI driver used the TX bits for the RX FIFO. This seems
uncritical for now since both are equals on my devices (VR9), but this
could cause problems on other SoCs.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
SVN-Revision: 47208
Diffstat (limited to 'target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch')
| -rw-r--r-- | target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch b/target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch index ed00b34336..9cc9349a71 100644 --- a/target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch +++ b/target/linux/lantiq/patches-3.18/0033-SPI-MIPS-lantiq-adds-spi-xway.patch @@ -913,7 +913,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org> + /* Read module capabilities */ + id = ltq_spi_reg_read(hw, LTQ_SPI_ID); + hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK; -+ hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK; ++ hw->rxfs = (id >> LTQ_SPI_ID_RXFS_SHIFT) & LTQ_SPI_ID_RXFS_MASK; + hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0; + + ltq_spi_config_mode_set(hw); |