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| author | John Crispin <john@openwrt.org> | 2013-09-17 21:46:10 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2013-09-17 21:46:10 +0000 |
| commit | 1878a3d6ab7e4296671eaa827623cc874d1f12c5 (patch) | |
| tree | 895fea96a0462bc19622aed65e9e179d22d61069 /target/linux/lantiq/patches-3.10/0016-MTD-lantiq-xway-the-latched-command-should-be-persis.patch | |
| parent | cd668944ef699762d4269ad71263ffe99c93ea8c (diff) | |
| download | master-31e0f0ae-1878a3d6ab7e4296671eaa827623cc874d1f12c5.tar.gz master-31e0f0ae-1878a3d6ab7e4296671eaa827623cc874d1f12c5.tar.bz2 master-31e0f0ae-1878a3d6ab7e4296671eaa827623cc874d1f12c5.zip | |
lantiq: add v3.10 patches
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 38031
Diffstat (limited to 'target/linux/lantiq/patches-3.10/0016-MTD-lantiq-xway-the-latched-command-should-be-persis.patch')
| -rw-r--r-- | target/linux/lantiq/patches-3.10/0016-MTD-lantiq-xway-the-latched-command-should-be-persis.patch | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-3.10/0016-MTD-lantiq-xway-the-latched-command-should-be-persis.patch b/target/linux/lantiq/patches-3.10/0016-MTD-lantiq-xway-the-latched-command-should-be-persis.patch new file mode 100644 index 0000000000..bd38b07ad6 --- /dev/null +++ b/target/linux/lantiq/patches-3.10/0016-MTD-lantiq-xway-the-latched-command-should-be-persis.patch @@ -0,0 +1,49 @@ +From 1e4f35a2ec92447818e89432ec297f14ac66c7c1 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Sun, 28 Jul 2013 18:06:39 +0200 +Subject: [PATCH 16/34] MTD: lantiq: xway: the latched command should be + persistent + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + drivers/mtd/nand/xway_nand.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c +index 169a91d..7f2bdd1 100644 +--- a/drivers/mtd/nand/xway_nand.c ++++ b/drivers/mtd/nand/xway_nand.c +@@ -54,6 +54,8 @@ + #define NAND_CON_CSMUX (1 << 1) + #define NAND_CON_NANDM 1 + ++static u32 xway_latchcmd; ++ + static void xway_reset_chip(struct nand_chip *chip) + { + unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W; +@@ -94,17 +96,15 @@ static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) + unsigned long flags; + + if (ctrl & NAND_CTRL_CHANGE) { +- nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR); + if (ctrl & NAND_CLE) +- nandaddr |= NAND_WRITE_CMD; +- else +- nandaddr |= NAND_WRITE_ADDR; +- this->IO_ADDR_W = (void __iomem *) nandaddr; ++ xway_latchcmd = NAND_WRITE_CMD; ++ else if (ctrl & NAND_ALE) ++ xway_latchcmd = NAND_WRITE_ADDR; + } + + if (cmd != NAND_CMD_NONE) { + spin_lock_irqsave(&ebu_lock, flags); +- writeb(cmd, this->IO_ADDR_W); ++ writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd)); + while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; + spin_unlock_irqrestore(&ebu_lock, flags); +-- +1.7.10.4 + |