ipq806x: Add support for IPQ806x chip family

Patches are generated using the "format-patch" command from the
following location:
*https://www.codeaurora.org/cgit/quic/kernel/galak-msm/log/?h=apq_ipq_base
*rev=0771849495b4128cac2faf7d49c85c729fc48b20
Patches numbered 76/77/102/103 have already been integrated in 3.14.12,
so they're not in this list.

All these patches are either integrated are pending integration into
kernel.org, therefore these patches should go away once the kernel
gets upgraded to 3.16.

Support is currently limited to AP148 board but can be extended to other
platforms in the future.

These changes do not cover ethernet connectivity.

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

SVN-Revision: 42334

1 files changed, 216 insertions, 0 deletions

diff --git a/target/linux/ipq806x/patches/0096-ARM-dts-qcom-Add-APQ8084-SoC-support.patch b/target/linux/ipq806x/patches/0096-ARM-dts-qcom-Add-APQ8084-SoC-support.patch
new file mode 100644
index 0000000000..87d70a54e5
--- /dev/null
+++ b/target/linux/ipq806x/patches/0096-ARM-dts-qcom-Add-APQ8084-SoC-support.patch
@@ -0,0 +1,216 @@
+From 8c52931421759b70fc37771be3390813a2a2f9f5 Mon Sep 17 00:00:00 2001
+From: Georgi Djakov <gdjakov@mm-sol.com>
+Date: Fri, 23 May 2014 18:12:29 +0300
+Subject: [PATCH 096/182] ARM: dts: qcom: Add APQ8084 SoC support
+
+Add support for the Qualcomm Snapdragon 805 APQ8084 SoC. It is
+used on APQ8084-MTP and other boards.
+
+Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
+Signed-off-by: Kumar Gala <galak@codeaurora.org>
+---
+ arch/arm/boot/dts/qcom-apq8084.dtsi |  179 +++++++++++++++++++++++++++++++++++
+ arch/arm/mach-qcom/board.c          |    1 +
+ 2 files changed, 180 insertions(+)
+ create mode 100644 arch/arm/boot/dts/qcom-apq8084.dtsi
+
+diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
+new file mode 100644
+index 0000000..e3e009a
+--- /dev/null
++++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
+@@ -0,0 +1,179 @@
++/dts-v1/;
++
++#include "skeleton.dtsi"
++
++/ {
++	model = "Qualcomm APQ 8084";
++	compatible = "qcom,apq8084";
++	interrupt-parent = <&intc>;
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		cpu@0 {
++			device_type = "cpu";
++			compatible = "qcom,krait";
++			reg = <0>;
++			enable-method = "qcom,kpss-acc-v2";
++			next-level-cache = <&L2>;
++			qcom,acc = <&acc0>;
++		};
++
++		cpu@1 {
++			device_type = "cpu";
++			compatible = "qcom,krait";
++			reg = <1>;
++			enable-method = "qcom,kpss-acc-v2";
++			next-level-cache = <&L2>;
++			qcom,acc = <&acc1>;
++		};
++
++		cpu@2 {
++			device_type = "cpu";
++			compatible = "qcom,krait";
++			reg = <2>;
++			enable-method = "qcom,kpss-acc-v2";
++			next-level-cache = <&L2>;
++			qcom,acc = <&acc2>;
++		};
++
++		cpu@3 {
++			device_type = "cpu";
++			compatible = "qcom,krait";
++			reg = <3>;
++			enable-method = "qcom,kpss-acc-v2";
++			next-level-cache = <&L2>;
++			qcom,acc = <&acc3>;
++		};
++
++		L2: l2-cache {
++			compatible = "qcom,arch-cache";
++			cache-level = <2>;
++			qcom,saw = <&saw_l2>;
++		};
++	};
++
++	cpu-pmu {
++		compatible = "qcom,krait-pmu";
++		interrupts = <1 7 0xf04>;
++	};
++
++	timer {
++		compatible = "arm,armv7-timer";
++		interrupts = <1 2 0xf08>,
++			     <1 3 0xf08>,
++			     <1 4 0xf08>,
++			     <1 1 0xf08>;
++		clock-frequency = <19200000>;
++	};
++
++	soc: soc {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges;
++		compatible = "simple-bus";
++
++		intc: interrupt-controller@f9000000 {
++			compatible = "qcom,msm-qgic2";
++			interrupt-controller;
++			#interrupt-cells = <3>;
++			reg = <0xf9000000 0x1000>,
++			      <0xf9002000 0x1000>;
++		};
++
++		timer@f9020000 {
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges;
++			compatible = "arm,armv7-timer-mem";
++			reg = <0xf9020000 0x1000>;
++			clock-frequency = <19200000>;
++
++			frame@f9021000 {
++				frame-number = <0>;
++				interrupts = <0 8 0x4>,
++					     <0 7 0x4>;
++				reg = <0xf9021000 0x1000>,
++				      <0xf9022000 0x1000>;
++			};
++
++			frame@f9023000 {
++				frame-number = <1>;
++				interrupts = <0 9 0x4>;
++				reg = <0xf9023000 0x1000>;
++				status = "disabled";
++			};
++
++			frame@f9024000 {
++				frame-number = <2>;
++				interrupts = <0 10 0x4>;
++				reg = <0xf9024000 0x1000>;
++				status = "disabled";
++			};
++
++			frame@f9025000 {
++				frame-number = <3>;
++				interrupts = <0 11 0x4>;
++				reg = <0xf9025000 0x1000>;
++				status = "disabled";
++			};
++
++			frame@f9026000 {
++				frame-number = <4>;
++				interrupts = <0 12 0x4>;
++				reg = <0xf9026000 0x1000>;
++				status = "disabled";
++			};
++
++			frame@f9027000 {
++				frame-number = <5>;
++				interrupts = <0 13 0x4>;
++				reg = <0xf9027000 0x1000>;
++				status = "disabled";
++			};
++
++			frame@f9028000 {
++				frame-number = <6>;
++				interrupts = <0 14 0x4>;
++				reg = <0xf9028000 0x1000>;
++				status = "disabled";
++			};
++		};
++
++		saw_l2: regulator@f9012000 {
++			compatible = "qcom,saw2";
++			reg = <0xf9012000 0x1000>;
++			regulator;
++		};
++
++		acc0: clock-controller@f9088000 {
++			compatible = "qcom,kpss-acc-v2";
++			reg = <0xf9088000 0x1000>,
++			      <0xf9008000 0x1000>;
++		};
++
++		acc1: clock-controller@f9098000 {
++			compatible = "qcom,kpss-acc-v2";
++			reg = <0xf9098000 0x1000>,
++			      <0xf9008000 0x1000>;
++		};
++
++		acc2: clock-controller@f90a8000 {
++			compatible = "qcom,kpss-acc-v2";
++			reg = <0xf90a8000 0x1000>,
++			      <0xf9008000 0x1000>;
++		};
++
++		acc3: clock-controller@f90b8000 {
++			compatible = "qcom,kpss-acc-v2";
++			reg = <0xf90b8000 0x1000>,
++			      <0xf9008000 0x1000>;
++		};
++
++		restart@fc4ab000 {
++			compatible = "qcom,pshold";
++			reg = <0xfc4ab000 0x4>;
++		};
++	};
++};
+diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
+index 350fa8d..c437a99 100644
+--- a/arch/arm/mach-qcom/board.c
++++ b/arch/arm/mach-qcom/board.c
+@@ -17,6 +17,7 @@
+ static const char * const qcom_dt_match[] __initconst = {
+ 	"qcom,apq8064",
+ 	"qcom,apq8074-dragonboard",
++	"qcom,apq8084",
+ 	"qcom,msm8660-surf",
+ 	"qcom,msm8960-cdp",
+ 	NULL
+-- 
+1.7.10.4
+