ipq806x: Add support for IPQ806x chip family

Patches are generated using the "format-patch" command from the
following location:
*https://www.codeaurora.org/cgit/quic/kernel/galak-msm/log/?h=apq_ipq_base
*rev=0771849495b4128cac2faf7d49c85c729fc48b20
Patches numbered 76/77/102/103 have already been integrated in 3.14.12,
so they're not in this list.

All these patches are either integrated are pending integration into
kernel.org, therefore these patches should go away once the kernel
gets upgraded to 3.16.

Support is currently limited to AP148 board but can be extended to other
platforms in the future.

These changes do not cover ethernet connectivity.

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

SVN-Revision: 42334

1 files changed, 95 insertions, 0 deletions

diff --git a/target/linux/ipq806x/patches/0031-pinctrl-msm-Remove-impossible-WARN_ON-s.patch b/target/linux/ipq806x/patches/0031-pinctrl-msm-Remove-impossible-WARN_ON-s.patch
new file mode 100644
index 0000000000..61c8ac1b2a
--- /dev/null
+++ b/target/linux/ipq806x/patches/0031-pinctrl-msm-Remove-impossible-WARN_ON-s.patch
@@ -0,0 +1,95 @@
+From 286113578287b9c7619b4104864cffb91820f49d Mon Sep 17 00:00:00 2001
+From: Stephen Boyd <sboyd@codeaurora.org>
+Date: Thu, 6 Mar 2014 22:44:45 -0800
+Subject: [PATCH 031/182] pinctrl: msm: Remove impossible WARN_ON()s
+
+All these functions are limited in what they can pass as the gpio
+or irq number to whatever is setup during probe. Remove the
+checks.
+
+Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-msm.c |   16 ----------------
+ 1 file changed, 16 deletions(-)
+
+diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c
+index 87f6c3c..ab46e3a 100644
+--- a/drivers/pinctrl/pinctrl-msm.c
++++ b/drivers/pinctrl/pinctrl-msm.c
+@@ -401,8 +401,6 @@ static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+ 	u32 val;
+ 
+ 	g = &pctrl->soc->groups[offset];
+-	if (WARN_ON(g->io_reg < 0))
+-		return -EINVAL;
+ 
+ 	spin_lock_irqsave(&pctrl->lock, flags);
+ 
+@@ -423,8 +421,6 @@ static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, in
+ 	u32 val;
+ 
+ 	g = &pctrl->soc->groups[offset];
+-	if (WARN_ON(g->io_reg < 0))
+-		return -EINVAL;
+ 
+ 	spin_lock_irqsave(&pctrl->lock, flags);
+ 
+@@ -451,8 +447,6 @@ static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
+ 	u32 val;
+ 
+ 	g = &pctrl->soc->groups[offset];
+-	if (WARN_ON(g->io_reg < 0))
+-		return -EINVAL;
+ 
+ 	val = readl(pctrl->regs + g->io_reg);
+ 	return !!(val & BIT(g->in_bit));
+@@ -466,8 +460,6 @@ static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+ 	u32 val;
+ 
+ 	g = &pctrl->soc->groups[offset];
+-	if (WARN_ON(g->io_reg < 0))
+-		return;
+ 
+ 	spin_lock_irqsave(&pctrl->lock, flags);
+ 
+@@ -616,8 +608,6 @@ static void msm_gpio_irq_mask(struct irq_data *d)
+ 
+ 	pctrl = irq_data_get_irq_chip_data(d);
+ 	g = &pctrl->soc->groups[d->hwirq];
+-	if (WARN_ON(g->intr_cfg_reg < 0))
+-		return;
+ 
+ 	spin_lock_irqsave(&pctrl->lock, flags);
+ 
+@@ -639,8 +629,6 @@ static void msm_gpio_irq_unmask(struct irq_data *d)
+ 
+ 	pctrl = irq_data_get_irq_chip_data(d);
+ 	g = &pctrl->soc->groups[d->hwirq];
+-	if (WARN_ON(g->intr_status_reg < 0))
+-		return;
+ 
+ 	spin_lock_irqsave(&pctrl->lock, flags);
+ 
+@@ -666,8 +654,6 @@ static void msm_gpio_irq_ack(struct irq_data *d)
+ 
+ 	pctrl = irq_data_get_irq_chip_data(d);
+ 	g = &pctrl->soc->groups[d->hwirq];
+-	if (WARN_ON(g->intr_status_reg < 0))
+-		return;
+ 
+ 	spin_lock_irqsave(&pctrl->lock, flags);
+ 
+@@ -692,8 +678,6 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
+ 
+ 	pctrl = irq_data_get_irq_chip_data(d);
+ 	g = &pctrl->soc->groups[d->hwirq];
+-	if (WARN_ON(g->intr_cfg_reg < 0))
+-		return -EINVAL;
+ 
+ 	spin_lock_irqsave(&pctrl->lock, flags);
+ 
+-- 
+1.7.10.4
+