ipq806x: update target to v3.18

Patches in the ipq806x/patches folder were out of tree in v3.14. The
newest patch at the time was from June, so we can safely assume that
either the patches have been merged, or they have been rejected for
a good reason. If patches are seen missing, we'll cherry-pick them
on a per-needed basis.

This new kernel have been tested on AP148, which seems to works fine.

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>

SVN-Revision: 44386

1 files changed, 0 insertions, 73 deletions

diff --git a/target/linux/ipq806x/patches/0006-clocksource-qcom-split-building-of-legacy-vs-multipl.patch b/target/linux/ipq806x/patches/0006-clocksource-qcom-split-building-of-legacy-vs-multipl.patch
deleted file mode 100644
index 79603f89c9..0000000000
--- a/target/linux/ipq806x/patches/0006-clocksource-qcom-split-building-of-legacy-vs-multipl.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From 085d4b834dfced8580aab74707e30699b63e7c36 Mon Sep 17 00:00:00 2001
-From: Kumar Gala <galak@codeaurora.org>
-Date: Wed, 29 Jan 2014 17:01:37 -0600
-Subject: [PATCH 006/182] clocksource: qcom: split building of legacy vs
- multiplatform support
-
-The majority of the clocksource code for the Qualcomm platform is shared
-between newer (multiplatform) and older platforms.  However there is a bit
-of code that isn't, so only build it for the appropriate config.
-
-Acked-by: Olof Johansson <olof@lixom.net>
-Signed-off-by: Kumar Gala <galak@codeaurora.org>
----
- drivers/clocksource/qcom-timer.c |   23 ++++++++++++-----------
- 1 file changed, 12 insertions(+), 11 deletions(-)
-
---- a/drivers/clocksource/qcom-timer.c
-+++ b/drivers/clocksource/qcom-timer.c
-@@ -106,15 +106,6 @@ static notrace cycle_t msm_read_timer_co
- 	return readl_relaxed(source_base + TIMER_COUNT_VAL);
- }
- 
--static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
--{
--	/*
--	 * Shift timer count down by a constant due to unreliable lower bits
--	 * on some targets.
--	 */
--	return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
--}
--
- static struct clocksource msm_clocksource = {
- 	.name	= "dg_timer",
- 	.rating	= 300,
-@@ -228,7 +219,7 @@ err:
- 	sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
- }
- 
--#ifdef CONFIG_OF
-+#ifdef CONFIG_ARCH_QCOM
- static void __init msm_dt_timer_init(struct device_node *np)
- {
- 	u32 freq;
-@@ -281,7 +272,7 @@ static void __init msm_dt_timer_init(str
- }
- CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
- CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
--#endif
-+#else
- 
- static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
- 				u32 sts)
-@@ -301,6 +292,15 @@ static int __init msm_timer_map(phys_add
- 	return 0;
- }
- 
-+static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
-+{
-+	/*
-+	 * Shift timer count down by a constant due to unreliable lower bits
-+	 * on some targets.
-+	 */
-+	return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
-+}
-+
- void __init msm7x01_timer_init(void)
- {
- 	struct clocksource *cs = &msm_clocksource;
-@@ -327,3 +327,4 @@ void __init qsd8x50_timer_init(void)
- 		return;
- 	msm_timer_init(19200000 / 4, 32, 7, false);
- }
-+#endif