diff options
| author | Luka Perkov <luka@openwrt.org> | 2014-08-08 13:38:27 +0000 |
|---|---|---|
| committer | Luka Perkov <luka@openwrt.org> | 2014-08-08 13:38:27 +0000 |
| commit | d5f94a4122193f738517e1c960be2ff1d60848f4 (patch) | |
| tree | 8cf41189ed53f399c6744f99e2d39637d4a40b68 /target/linux/imx6 | |
| parent | 2b6d364a2d210f4eeb8bdbd91367f1068982bc98 (diff) | |
| download | master-31e0f0ae-d5f94a4122193f738517e1c960be2ff1d60848f4.tar.gz master-31e0f0ae-d5f94a4122193f738517e1c960be2ff1d60848f4.tar.bz2 master-31e0f0ae-d5f94a4122193f738517e1c960be2ff1d60848f4.zip | |
imx6: backport IMX6DL DVFS support from 3.15
This allows dynamic voltage and frequency scaling to work for IMX6DL CPU's.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 42072
Diffstat (limited to 'target/linux/imx6')
| -rw-r--r-- | target/linux/imx6/patches-3.14/0004-ARM-dts-imx6dl-enable-cpufreq-support.patch | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/target/linux/imx6/patches-3.14/0004-ARM-dts-imx6dl-enable-cpufreq-support.patch b/target/linux/imx6/patches-3.14/0004-ARM-dts-imx6dl-enable-cpufreq-support.patch new file mode 100644 index 0000000000..be5eefbfa5 --- /dev/null +++ b/target/linux/imx6/patches-3.14/0004-ARM-dts-imx6dl-enable-cpufreq-support.patch @@ -0,0 +1,47 @@ +From 978ed904c17cd39700a5e1f95ee29ef4fee08ce9 Mon Sep 17 00:00:00 2001 +From: Anson Huang <b20788@freescale.com> +Date: Thu, 19 Dec 2013 10:02:10 -0500 +Subject: [PATCH] ARM: dts: imx6dl: enable cpufreq support + +This patch adds cpufreq dts for i.mx6dl to support cpufreq driver. + +Signed-off-by: Anson Huang <b20788@freescale.com> +Signed-off-by: Shawn Guo <shawn.guo@linaro.org> +--- + arch/arm/boot/dts/imx6dl.dtsi | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi +index 80d0abe..9c4942f 100644 +--- a/arch/arm/boot/dts/imx6dl.dtsi ++++ b/arch/arm/boot/dts/imx6dl.dtsi +@@ -22,6 +22,26 @@ + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; ++ operating-points = < ++ /* kHz uV */ ++ 996000 1275000 ++ 792000 1175000 ++ 396000 1075000 ++ >; ++ fsl,soc-operating-points = < ++ /* ARM kHz SOC-PU uV */ ++ 996000 1175000 ++ 792000 1175000 ++ 396000 1175000 ++ >; ++ clock-latency = <61036>; /* two CLK32 periods */ ++ clocks = <&clks 104>, <&clks 6>, <&clks 16>, ++ <&clks 17>, <&clks 170>; ++ clock-names = "arm", "pll2_pfd2_396m", "step", ++ "pll1_sw", "pll1_sys"; ++ arm-supply = <®_arm>; ++ pu-supply = <®_pu>; ++ soc-supply = <®_soc>; + }; + + cpu@1 { +-- +2.0.3 + |