diff options
| author | John Crispin <john@openwrt.org> | 2009-10-02 08:09:27 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2009-10-02 08:09:27 +0000 |
| commit | 696c29fa4d08971bdfff339e0a486a61441576e8 (patch) | |
| tree | 89822e8a29e60514cedb7fd9427070de042a4388 /target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch | |
| parent | b88e08839a8f61f2c9829ba6c9e37b4d60b84b62 (diff) | |
| download | master-31e0f0ae-696c29fa4d08971bdfff339e0a486a61441576e8.tar.gz master-31e0f0ae-696c29fa4d08971bdfff339e0a486a61441576e8.tar.bz2 master-31e0f0ae-696c29fa4d08971bdfff339e0a486a61441576e8.zip | |
bump ifxmips to .30
SVN-Revision: 17817
Diffstat (limited to 'target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch')
| -rw-r--r-- | target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch b/target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch new file mode 100644 index 0000000000..49ff663105 --- /dev/null +++ b/target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch @@ -0,0 +1,35 @@ +Index: linux-2.6.30.5/arch/mips/kernel/cevt-r4k.c +=================================================================== +--- linux-2.6.30.5.orig/arch/mips/kernel/cevt-r4k.c 2009-08-16 23:19:38.000000000 +0200 ++++ linux-2.6.30.5/arch/mips/kernel/cevt-r4k.c 2009-09-02 18:26:26.000000000 +0200 +@@ -21,6 +21,22 @@ + + #ifndef CONFIG_MIPS_MT_SMTC + ++/* ++ * Compare interrupt can be routed and latched outside the core, ++ * so a single execution hazard barrier may not be enough to give ++ * it time to clear as seen in the Cause register. 4 time the ++ * pipeline depth seems reasonably conservative, and empirically ++ * works better in configurations with high CPU/bus clock ratios. ++ */ ++ ++#define compare_change_hazard() \ ++ do { \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ } while (0) ++ + static int mips_next_event(unsigned long delta, + struct clock_event_device *evt) + { +@@ -30,6 +46,7 @@ + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); ++ compare_change_hazard(); + res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; + return res; + } |