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| author | Felix Fietkau <nbd@openwrt.org> | 2016-01-18 22:38:09 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2016-01-18 22:38:09 +0000 |
| commit | 136747c564c3a73b28eb9283d4d97f1c07d101a5 (patch) | |
| tree | 515fe87a028a4672909f5ba12925925cfe976752 /target/linux/cns3xxx | |
| parent | 8ecfa0e773f3aec21ab793e4f5588a2c4347ebb9 (diff) | |
| download | master-31e0f0ae-136747c564c3a73b28eb9283d4d97f1c07d101a5.tar.gz master-31e0f0ae-136747c564c3a73b28eb9283d4d97f1c07d101a5.tar.bz2 master-31e0f0ae-136747c564c3a73b28eb9283d4d97f1c07d101a5.zip | |
cns3xxx: clean up SMP related code
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 48332
Diffstat (limited to 'target/linux/cns3xxx')
| -rw-r--r-- | target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S | 5 | ||||
| -rw-r--r-- | target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c | 18 |
2 files changed, 6 insertions, 17 deletions
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S index 3b46bdc324..f0da8ec0a5 100644 --- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S +++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S @@ -13,8 +13,6 @@ #include <linux/linkage.h> #include <linux/init.h> - __CPUINIT - /* * CNS3XXX specific entry point for secondary CPUs. This provides * a "holding pen" into which all secondary cores are held until we're @@ -36,7 +34,8 @@ pen: ldr r7, [r6] * should now contain the SVC stack for this core */ b secondary_startup +ENDPROC(cns3xxx_secondary_startup) - .align + .align 2 1: .long . .long pen_release diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c index 53598857fd..cb81d1e752 100644 --- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c +++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c @@ -66,7 +66,7 @@ extern unsigned char cns3xxx_fiq_start, cns3xxx_fiq_end; #define SCU_CPU_STATUS 0x08 static void __iomem *scu_base; -static inline void __cpuinit cns3xxx_set_fiq_regs(unsigned int cpu) +static inline void cns3xxx_set_fiq_regs(unsigned int cpu) { struct pt_regs FIQ_regs; struct fiq_req *fiq_req = &per_cpu(fiq_data, !cpu); @@ -101,7 +101,7 @@ static void __init cns3xxx_init_fiq(void) * observers, irrespective of whether they're taking part in coherency * or not. This is necessary for the hotplug code to work reliably. */ -static void __cpuinit write_pen_release(int val) +static void write_pen_release(int val) { pen_release = val; smp_wmb(); @@ -111,7 +111,7 @@ static void __cpuinit write_pen_release(int val) static DEFINE_SPINLOCK(boot_lock); -static void __cpuinit cns3xxx_secondary_init(unsigned int cpu) +static void cns3xxx_secondary_init(unsigned int cpu) { /* * Setup Secondary Core FIQ regs @@ -131,7 +131,7 @@ static void __cpuinit cns3xxx_secondary_init(unsigned int cpu) spin_unlock(&boot_lock); } -static int __cpuinit cns3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int cns3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; @@ -202,16 +202,6 @@ static void __init cns3xxx_smp_init_cpus(void) static void __init cns3xxx_smp_prepare_cpus(unsigned int max_cpus) { - int i; - - /* - * Initialise the present map, which describes the set of CPUs - * actually populated at the present time. - */ - for (i = 0; i < max_cpus; i++) { - set_cpu_present(i, true); - } - /* * enable SCU */ |