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| author | Felix Fietkau <nbd@openwrt.org> | 2013-03-09 18:51:46 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2013-03-09 18:51:46 +0000 |
| commit | 95f14d052a7439c60e35a6d910d6bd3de023907c (patch) | |
| tree | 83b1039c3c9d0ff8d8b842d1ec5fc4a392a3a7d2 /target/linux/cns3xxx | |
| parent | 85348d602e2c4b383fa0bec95fb97d9d79094743 (diff) | |
| download | master-31e0f0ae-95f14d052a7439c60e35a6d910d6bd3de023907c.tar.gz master-31e0f0ae-95f14d052a7439c60e35a6d910d6bd3de023907c.tar.bz2 master-31e0f0ae-95f14d052a7439c60e35a6d910d6bd3de023907c.zip | |
cns3xxx: add linux 3.8 support and use it by default
SVN-Revision: 35908
Diffstat (limited to 'target/linux/cns3xxx')
31 files changed, 1543 insertions, 25 deletions
diff --git a/target/linux/cns3xxx/Makefile b/target/linux/cns3xxx/Makefile index 50c0e948f2..aeca8f6789 100644 --- a/target/linux/cns3xxx/Makefile +++ b/target/linux/cns3xxx/Makefile @@ -13,7 +13,7 @@ FEATURES:=squashfs fpu gpio pcie usb usbgadget CFLAGS:=-Os -pipe -march=armv6k -mtune=mpcore -mfloat-abi=softfp -mfpu=vfp -fno-caller-saves MAINTAINER:=Imre Kaloz <kaloz@openwrt.org> -LINUX_VERSION:=3.3.8 +LINUX_VERSION:=3.8.2 include $(INCLUDE_DIR)/target.mk diff --git a/target/linux/cns3xxx/config-3.8 b/target/linux/cns3xxx/config-3.8 new file mode 100644 index 0000000000..c3f4fb1646 --- /dev/null +++ b/target/linux/cns3xxx/config-3.8 @@ -0,0 +1,226 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_ARCH_CNS3XXX=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_REQUIRE_GPIOLIB=y +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARCH_VT8500_SINGLE is not set +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARM=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARM_GIC=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_NR_BANKS=8 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_THUMB=y +CONFIG_ATA=y +CONFIG_ATAGS=y +# CONFIG_ATA_SFF is not set +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BLK_DEV_SD=y +CONFIG_CACHE_L2X0=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CNS3XXX_ETH=y +CONFIG_CPU_32v6=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_ABRT_EV6=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_V6K=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEBUG_LL_UART_NONE=y +# CONFIG_DEBUG_USER is not set +CONFIG_DECOMPRESS_LZMA=y +# CONFIG_DWC_DEBUG is not set +# CONFIG_DWC_DEVICE_ONLY is not set +# CONFIG_DWC_HOST_ONLY is not set +CONFIG_DWC_OTG_MODE=y +CONFIG_EARLY_PRINTK=y +CONFIG_EEPROM_AT24=y +CONFIG_FIQ=y +CONFIG_FRAME_POINTER=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_SYSFS=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAVE_AOUT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IRQ_WORK=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HWMON=y +CONFIG_HW_RANDOM=m +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_CNS3XXX=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQ_DOMAIN=y +CONFIG_KTIME_SCALAR=y +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_TRIGGER_NETDEV is not set +CONFIG_LOCAL_TIMERS=y +CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MACH_CNS3420VB is not set +CONFIG_MACH_GW2388=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_CNS3XXX=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MPCORE_WATCHDOG=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NET_VENDOR_CAVIUM=y +CONFIG_NLS=y +CONFIG_NR_CPUS=2 +CONFIG_NTP_PPS=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PCI=y +CONFIG_PCI_DISABLE_COMMON_QUIRKS=y +CONFIG_PCI_DOMAINS=y +CONFIG_PERCPU_RWSEM=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PHYLIB=y +CONFIG_PL310_ERRATA_588369=y +CONFIG_PL310_ERRATA_727915=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_PPS=y +CONFIG_PPS_CLIENT_GPIO=y +# CONFIG_PREEMPT_RCU is not set +CONFIG_RAID_ATTRS=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1672=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_SCSI=y +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SENSORS_AD7418=y +CONFIG_SENSORS_GSC=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_CNS3XXX=y +CONFIG_SPI_MASTER=y +# CONFIG_STAGING is not set +CONFIG_STOP_MACHINE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TREE_RCU=y +CONFIG_UID16=y +CONFIG_UIDGID_CONVERTED=y +CONFIG_USB=y +# CONFIG_USB_AMD5536UDC is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_ARCH_HAS_XHCI=y +CONFIG_USB_CNS3XXX_EHCI=y +CONFIG_USB_CNS3XXX_OHCI=y +CONFIG_USB_COMMON=y +CONFIG_USB_DWC_OTG=y +# CONFIG_USB_EG20T is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_EHCI_PCI=y +# CONFIG_USB_ETH is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GOKU is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_SUPPORT=y +# CONFIG_USB_UHCI_HCD is not set +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_VFP=y +CONFIG_WATCHDOG_NOWAYOUT=y +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S index 456fd67f97..3b46bdc324 100644 --- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S +++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/headsmp.S @@ -13,7 +13,7 @@ #include <linux/linkage.h> #include <linux/init.h> - __INIT + __CPUINIT /* * CNS3XXX specific entry point for secondary CPUs. This provides diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c index 16ad562651..77ac97a20c 100644 --- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c +++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/platsmp.c @@ -49,12 +49,6 @@ struct cpu_cache_fns cpu_cache_save; #define SCU_CPU_STATUS 0x08 static void __iomem *scu_base; -/* - * control for which core is the next to come out of the secondary - * boot "holding pen" - */ -volatile int __cpuinitdata pen_release = -1; - static void __init cns3xxx_set_fiq_regs(void) { struct pt_regs FIQ_regs; @@ -108,7 +102,7 @@ static void __cpuinit write_pen_release(int val) static DEFINE_SPINLOCK(boot_lock); -void __cpuinit platform_secondary_init(unsigned int cpu) +static void __cpuinit cns3xxx_secondary_init(unsigned int cpu) { /* * if any interrupts are already enabled for the primary @@ -143,7 +137,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) spin_unlock(&boot_lock); } -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +static int __cpuinit cns3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; @@ -192,7 +186,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * Initialise the CPU possible map early - this describes the CPUs * which may be present or become present in the system. */ -void __init smp_init_cpus(void) +static void __init cns3xxx_smp_init_cpus(void) { unsigned int i, ncores; unsigned int status; @@ -214,7 +208,7 @@ void __init smp_init_cpus(void) set_smp_cross_call(gic_raise_softirq); } -void __init platform_smp_prepare_cpus(unsigned int max_cpus) +static void __init cns3xxx_smp_prepare_cpus(unsigned int max_cpus) { int i; @@ -348,3 +342,10 @@ void smp_dma_flush_range(const void *start, const void *end) } raw_local_irq_restore(flags); } + +struct smp_operations cns3xxx_smp_ops __initdata = { + .smp_init_cpus = cns3xxx_smp_init_cpus, + .smp_prepare_cpus = cns3xxx_smp_prepare_cpus, + .smp_secondary_init = cns3xxx_secondary_init, + .smp_boot_secondary = cns3xxx_boot_secondary, +}; diff --git a/target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c b/target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c index f578eac054..c3fd7c8972 100644 --- a/target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c +++ b/target/linux/cns3xxx/files/drivers/i2c/busses/i2c-cns3xxx.c @@ -259,7 +259,7 @@ static irqreturn_t cns3xxx_i2c_isr(int irq, void *dev_id) return IRQ_HANDLED; } -static int __devinit cns3xxx_i2c_probe(struct platform_device *pdev) +static int cns3xxx_i2c_probe(struct platform_device *pdev) { struct cns3xxx_i2c *i2c; struct resource *res, *res2; @@ -331,7 +331,7 @@ static int __devinit cns3xxx_i2c_probe(struct platform_device *pdev) return ret; } -static int __devexit cns3xxx_i2c_remove(struct platform_device *pdev) +static int cns3xxx_i2c_remove(struct platform_device *pdev) { struct cns3xxx_i2c *i2c = platform_get_drvdata(pdev); struct resource *res; diff --git a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c index a9edefe4bb..959589dc14 100644 --- a/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c +++ b/target/linux/cns3xxx/files/drivers/net/ethernet/cavium/cns3xxx_eth.c @@ -629,7 +629,7 @@ static int eth_poll(struct napi_struct *napi, int budget) dma_unmap_single(NULL, rx_ring->phys_tab[i], RX_SEGMENT_MRU, DMA_FROM_DEVICE); - skb = build_skb(rx_ring->buff_tab[i]); + skb = build_skb(rx_ring->buff_tab[i], 0); if (!skb) break; @@ -1153,7 +1153,7 @@ static const struct net_device_ops cns3xxx_netdev_ops = { .ndo_validate_addr = eth_validate_addr, }; -static int __devinit eth_init_one(struct platform_device *pdev) +static int eth_init_one(struct platform_device *pdev) { int i; struct port *port; @@ -1297,7 +1297,7 @@ err_free: return err; } -static int __devexit eth_remove_one(struct platform_device *pdev) +static int eth_remove_one(struct platform_device *pdev) { struct net_device *dev = platform_get_drvdata(pdev); struct sw *sw = netdev_priv(dev); diff --git a/target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c b/target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c index c66ef82447..2642639867 100644 --- a/target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c +++ b/target/linux/cns3xxx/files/drivers/spi/spi-cns3xxx.c @@ -324,7 +324,7 @@ static void __init cns3xxx_spi_initial(void) return; } -static int __devinit cns3xxx_spi_probe(struct platform_device *pdev) +static int cns3xxx_spi_probe(struct platform_device *pdev) { struct spi_master *master; struct cns3xxx_spi *hw; @@ -384,7 +384,7 @@ err_nomem: return err; } -static int __devexit cns3xxx_spi_remove(struct platform_device *dev) +static int cns3xxx_spi_remove(struct platform_device *dev) { struct cns3xxx_spi *hw = platform_get_drvdata(dev); @@ -419,7 +419,7 @@ static int cns3xxx_spi_resume(struct platform_device *pdev) static struct platform_driver cns3xxx_spi_driver = { .probe = cns3xxx_spi_probe, - .remove = __devexit_p(cns3xxx_spi_remove), + .remove = cns3xxx_spi_remove, .suspend = cns3xxx_spi_suspend, .resume = cns3xxx_spi_resume, .driver = { diff --git a/target/linux/cns3xxx/files/drivers/usb/dwc/otg_driver.c b/target/linux/cns3xxx/files/drivers/usb/dwc/otg_driver.c index 002c394797..f1fece8bf8 100644 --- a/target/linux/cns3xxx/files/drivers/usb/dwc/otg_driver.c +++ b/target/linux/cns3xxx/files/drivers/usb/dwc/otg_driver.c @@ -636,7 +636,7 @@ static int dwc_otg_driver_cleanup(struct platform_device *pdev) * * @param[in] lmdev lm_device definition */ -static int __devinit dwc_otg_driver_probe(struct platform_device *pdev) +static int dwc_otg_driver_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; int retval = 0; @@ -795,7 +795,7 @@ static int __devinit dwc_otg_driver_probe(struct platform_device *pdev) return retval; } -static int __devexit dwc_otg_driver_remove(struct platform_device *pdev) +static int dwc_otg_driver_remove(struct platform_device *pdev) { return dwc_otg_driver_cleanup(pdev); } @@ -803,7 +803,7 @@ static int __devexit dwc_otg_driver_remove(struct platform_device *pdev) static struct platform_driver dwc_otg_platform_driver = { .driver.name = "dwc_otg", .probe = dwc_otg_driver_probe, - .remove = __devexit_p(dwc_otg_driver_remove), + .remove = dwc_otg_driver_remove, }; static int __init dwc_otg_init_module(void) diff --git a/target/linux/cns3xxx/files/drivers/usb/dwc/otg_pcd.c b/target/linux/cns3xxx/files/drivers/usb/dwc/otg_pcd.c index 85c6fd9074..823989a6f5 100644 --- a/target/linux/cns3xxx/files/drivers/usb/dwc/otg_pcd.c +++ b/target/linux/cns3xxx/files/drivers/usb/dwc/otg_pcd.c @@ -820,7 +820,7 @@ struct free_param { dma_addr_t dma_addr; uint32_t size; }; -void free_list_agent_fn(void *data){ +static void free_list_agent_fn(struct work_struct *work) { struct list_head free_list; struct free_param *cur,*next; @@ -830,7 +830,7 @@ void free_list_agent_fn(void *data){ spin_unlock(&tofree_list_lock); list_for_each_entry_safe(cur,next,&free_list,list){ - if(cur==&free_list) break; + if(&cur->list==&free_list) break; dma_free_coherent(NULL,cur->size,cur->addr,cur->dma_addr); list_del(&cur->list); kfree(cur); diff --git a/target/linux/cns3xxx/patches-3.8/010-move_virtual_io_space.patch b/target/linux/cns3xxx/patches-3.8/010-move_virtual_io_space.patch new file mode 100644 index 0000000000..c7d89d5d0f --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/010-move_virtual_io_space.patch @@ -0,0 +1,198 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -24,17 +24,7 @@ static struct map_desc cns3xxx_io_desc[] + { + .virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE), +- .length = SZ_4K, +- .type = MT_DEVICE, +- }, { +- .virtual = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT, +- .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE), +- .length = SZ_4K, +- .type = MT_DEVICE, +- }, { +- .virtual = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT, +- .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE), +- .length = SZ_4K, ++ .length = SZ_8K, + .type = MT_DEVICE, + }, { + .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT, +--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h ++++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +@@ -20,22 +20,22 @@ + #define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */ + + #define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */ +-#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000 ++#define CNS3XXX_SWITCH_BASE_VIRT 0xFEF00000 + + #define CNS3XXX_PPE_BASE 0x70001000 /* HANT */ +-#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000 ++#define CNS3XXX_PPE_BASE_VIRT 0xFEF50000 + + #define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */ +-#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000 ++#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFEF60000 + + #define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */ +-#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000 ++#define CNS3XXX_SSP_BASE_VIRT 0xFEF01000 + + #define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */ +-#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000 ++#define CNS3XXX_DMC_BASE_VIRT 0xFEF02000 + + #define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */ +-#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000 ++#define CNS3XXX_SMC_BASE_VIRT 0xFEF03000 + + #define SMC_MEMC_STATUS_OFFSET 0x000 + #define SMC_MEMIF_CFG_OFFSET 0x004 +@@ -74,13 +74,13 @@ + #define SMC_PCELL_ID_3_OFFSET 0xFFC + + #define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ +-#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000 ++#define CNS3XXX_GPIOA_BASE_VIRT 0xFEF04000 + + #define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ +-#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000 ++#define CNS3XXX_GPIOB_BASE_VIRT 0xFEF05000 + + #define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ +-#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000 ++#define CNS3XXX_RTC_BASE_VIRT 0xFEF06000 + + #define RTC_SEC_OFFSET 0x00 + #define RTC_MIN_OFFSET 0x04 +@@ -94,10 +94,10 @@ + #define RTC_INTR_STS_OFFSET 0x34 + + #define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ +-#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */ ++#define CNS3XXX_MISC_BASE_VIRT 0xFEF07000 /* Misc Control */ + + #define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ +-#define CNS3XXX_PM_BASE_VIRT 0xFFF08000 ++#define CNS3XXX_PM_BASE_VIRT 0xFEF08000 + + #define PM_CLK_GATE_OFFSET 0x00 + #define PM_SOFT_RST_OFFSET 0x04 +@@ -109,28 +109,28 @@ + #define PM_PLL_HM_PD_OFFSET 0x1C + + #define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ +-#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000 ++#define CNS3XXX_UART0_BASE_VIRT 0xFEF09000 + + #define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ +-#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000 ++#define CNS3XXX_UART1_BASE_VIRT 0xFEF0A000 + + #define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */ +-#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000 ++#define CNS3XXX_UART2_BASE_VIRT 0xFEF0B000 + + #define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */ +-#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000 ++#define CNS3XXX_DMAC_BASE_VIRT 0xFEF0D000 + + #define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */ +-#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000 ++#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFEF0E000 + + #define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */ +-#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000 ++#define CNS3XXX_CRYPTO_BASE_VIRT 0xFEF0F000 + + #define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */ +-#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000 ++#define CNS3XXX_I2S_BASE_VIRT 0xFEF10000 + + #define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ +-#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800 ++#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFEF10800 + + #define TIMER1_COUNTER_OFFSET 0x00 + #define TIMER1_AUTO_RELOAD_OFFSET 0x04 +@@ -150,42 +150,42 @@ + #define TIMER_FREERUN_CONTROL_OFFSET 0x44 + + #define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */ +-#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000 ++#define CNS3XXX_HCIE_BASE_VIRT 0xFEF30000 + + #define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */ +-#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000 ++#define CNS3XXX_RAID_BASE_VIRT 0xFEF12000 + + #define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */ +-#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000 ++#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFEF13000 + + #define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */ +-#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000 ++#define CNS3XXX_CLCD_BASE_VIRT 0xFEF14000 + + #define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */ +-#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000 ++#define CNS3XXX_USBOTG_BASE_VIRT 0xFEF15000 + + #define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ + + #define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ + #define CNS3XXX_SATA2_SIZE SZ_16M +-#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000 ++#define CNS3XXX_SATA2_BASE_VIRT 0xFEF17000 + + #define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */ +-#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000 ++#define CNS3XXX_CAMERA_BASE_VIRT 0xFEF18000 + + #define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */ +-#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000 ++#define CNS3XXX_SDIO_BASE_VIRT 0xFEF19000 + + #define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */ +-#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000 ++#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFEF1A000 + + #define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */ +-#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000 ++#define CNS3XXX_2DG_BASE_VIRT 0xFEF1B000 + + #define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ + + #define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ +-#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000 ++#define CNS3XXX_L2C_BASE_VIRT 0xFEF27000 + + #define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */ + #define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000 +@@ -227,19 +227,19 @@ + * Testchip peripheral and fpga gic regions + */ + #define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ +-#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000 ++#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFEE00000 + + #define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ +-#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100 ++#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFEE00100 + + #define CNS3XXX_TC11MP_TWD_BASE 0x90000600 +-#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600 ++#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFEE00600 + + #define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ +-#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000 ++#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFEE01000 + + #define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ +-#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000 ++#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFEE02000 + + /* + * Misc block diff --git a/target/linux/cns3xxx/patches-3.8/015-clkdev_support.patch b/target/linux/cns3xxx/patches-3.8/015-clkdev_support.patch new file mode 100644 index 0000000000..15e301a45b --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/015-clkdev_support.patch @@ -0,0 +1,69 @@ +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -365,6 +365,7 @@ config ARCH_CNS3XXX + select MIGHT_HAVE_CACHE_L2X0 + select MIGHT_HAVE_PCI + select PCI_DOMAINS if PCI ++ select CLKDEV_LOOKUP + help + Support for Cavium Networks CNS3XXX platform. + +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -9,8 +9,11 @@ + */ + + #include <linux/init.h> ++#include <linux/export.h> + #include <linux/interrupt.h> + #include <linux/clockchips.h> ++#include <linux/clk.h> ++#include <linux/clkdev.h> + #include <linux/io.h> + #include <asm/mach/map.h> + #include <asm/mach/time.h> +@@ -20,6 +23,10 @@ + #include <mach/cns3xxx.h> + #include "core.h" + ++struct clk { ++ unsigned long rate; ++}; ++ + static struct map_desc cns3xxx_io_desc[] __initdata = { + { + .virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT, +@@ -277,3 +284,33 @@ void __init cns3xxx_l2x0_init(void) + } + + #endif /* CONFIG_CACHE_L2X0 */ ++ ++int clk_enable(struct clk *clk) ++{ ++ return 0; ++} ++EXPORT_SYMBOL(clk_enable); ++ ++void clk_disable(struct clk *clk) ++{ ++} ++EXPORT_SYMBOL(clk_disable); ++ ++unsigned long clk_get_rate(struct clk *clk) ++{ ++ return clk->rate; ++} ++EXPORT_SYMBOL(clk_get_rate); ++ ++static struct clk_lookup cns3xxx_clocks[] = { ++ { ++ /* TODO */ ++ }, ++}; ++ ++int __init cns3xxx_clocks_init(void) ++{ ++ clkdev_add_table(cns3xxx_clocks, ARRAY_SIZE(cns3xxx_clocks)); ++ return 0; ++} ++postcore_initcall(cns3xxx_clocks_init); diff --git a/target/linux/cns3xxx/patches-3.8/020-watchdog_support.patch b/target/linux/cns3xxx/patches-3.8/020-watchdog_support.patch new file mode 100644 index 0000000000..171e1f60ed --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/020-watchdog_support.patch @@ -0,0 +1,59 @@ +1. Made the connection between CNS3xxx SOCs(ARCH_CNS3xxx) and MPcore watchdog + since the CNS3xxx SOCs have ARM11 MPcore CPU. +2. Enable mpcore_watchdog option as module to default configuration at + arch/arm/configs/cns3420vb_defconfig. + +Signed-off-by: Tommy Lin <tommy.lin@caviumnetworks.com> + +--- +arch/arm/Kconfig | 1 + + arch/arm/configs/cns3420vb_defconfig | 2 ++ + arch/arm/mach-cns3xxx/cns3420vb.c | 22 ++++++++++++++++++++++ + 3 files changed, 25 insertions(+), 0 deletions(-) + +--- a/arch/arm/configs/cns3420vb_defconfig ++++ b/arch/arm/configs/cns3420vb_defconfig +@@ -53,6 +53,8 @@ CONFIG_LEGACY_PTY_COUNT=16 + # CONFIG_HW_RANDOM is not set + # CONFIG_HWMON is not set + # CONFIG_VGA_CONSOLE is not set ++CONFIG_WATCHDOG=y ++CONFIG_MPCORE_WATCHDOG=m + # CONFIG_HID_SUPPORT is not set + # CONFIG_USB_SUPPORT is not set + CONFIG_MMC=y +--- a/arch/arm/mach-cns3xxx/cns3420vb.c ++++ b/arch/arm/mach-cns3xxx/cns3420vb.c +@@ -208,10 +208,32 @@ static struct platform_device cns3xxx_us + }, + }; + ++/* Watchdog */ ++static struct resource cns3xxx_watchdog_resources[] = { ++ [0] = { ++ .start = CNS3XXX_TC11MP_TWD_BASE, ++ .end = CNS3XXX_TC11MP_TWD_BASE + PAGE_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_LOCALWDOG, ++ .end = IRQ_LOCALWDOG, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device cns3xxx_watchdog_device = { ++ .name = "mpcore_wdt", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(cns3xxx_watchdog_resources), ++ .resource = cns3xxx_watchdog_resources, ++}; ++ + /* + * Initialization + */ + static struct platform_device *cns3420_pdevs[] __initdata = { ++ &cns3xxx_watchdog_device, + &cns3420_nor_pdev, + &cns3xxx_usb_ehci_device, + &cns3xxx_usb_ohci_device, diff --git a/target/linux/cns3xxx/patches-3.8/021-cache_force_multi.patch b/target/linux/cns3xxx/patches-3.8/021-cache_force_multi.patch new file mode 100644 index 0000000000..536d9cad11 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/021-cache_force_multi.patch @@ -0,0 +1,35 @@ +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -366,6 +366,7 @@ config ARCH_CNS3XXX + select MIGHT_HAVE_PCI + select PCI_DOMAINS if PCI + select CLKDEV_LOOKUP ++ select CPU_CACHE_FORCE_MULTI + help + Support for Cavium Networks CNS3XXX platform. + +--- a/arch/arm/mm/Kconfig ++++ b/arch/arm/mm/Kconfig +@@ -496,6 +496,9 @@ config CPU_CACHE_VIPT + config CPU_CACHE_FA + bool + ++config CPU_CACHE_FORCE_MULTI ++ bool ++ + if MMU + # The copy-page model + config CPU_COPY_V4WT +--- a/arch/arm/include/asm/glue-cache.h ++++ b/arch/arm/include/asm/glue-cache.h +@@ -129,6 +129,10 @@ + #error Unknown cache maintenance model + #endif + ++#if defined(CONFIG_CPU_CACHE_FORCE_MULTI) && !defined(MULTI_CACHE) ++#define MULTI_CACHE 1 ++#endif ++ + #ifndef MULTI_CACHE + #define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all) + #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) diff --git a/target/linux/cns3xxx/patches-3.8/025-smp_support.patch b/target/linux/cns3xxx/patches-3.8/025-smp_support.patch new file mode 100644 index 0000000000..a9856451bf --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/025-smp_support.patch @@ -0,0 +1,38 @@ +--- a/arch/arm/mach-cns3xxx/Makefile ++++ b/arch/arm/mach-cns3xxx/Makefile +@@ -1,3 +1,5 @@ + obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o + obj-$(CONFIG_PCI) += pcie.o + obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o ++obj-$(CONFIG_SMP) += platsmp.o headsmp.o ++obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -367,6 +367,7 @@ config ARCH_CNS3XXX + select PCI_DOMAINS if PCI + select CLKDEV_LOOKUP + select CPU_CACHE_FORCE_MULTI ++ select HAVE_SMP + help + Support for Cavium Networks CNS3XXX platform. + +--- a/arch/arm/mach-cns3xxx/core.h ++++ b/arch/arm/mach-cns3xxx/core.h +@@ -11,6 +11,7 @@ + #ifndef __CNS3XXX_CORE_H + #define __CNS3XXX_CORE_H + ++extern struct smp_operations cns3xxx_smp_ops; + extern struct sys_timer cns3xxx_timer; + + #ifdef CONFIG_CACHE_L2X0 +--- a/arch/arm/mach-cns3xxx/laguna.c ++++ b/arch/arm/mach-cns3xxx/laguna.c +@@ -946,6 +946,7 @@ static int __init laguna_model_setup(voi + late_initcall(laguna_model_setup); + + MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform") ++ .smp = smp_ops(cns3xxx_smp_ops), + .atag_offset = 0x100, + .map_io = laguna_map_io, + .init_irq = cns3xxx_init_irq, diff --git a/target/linux/cns3xxx/patches-3.8/030-pcie_clock.patch b/target/linux/cns3xxx/patches-3.8/030-pcie_clock.patch new file mode 100644 index 0000000000..3734daf4c6 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/030-pcie_clock.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/mach-cns3xxx/pcie.c ++++ b/arch/arm/mach-cns3xxx/pcie.c +@@ -370,8 +370,6 @@ static int __init cns3xxx_pcie_init(void + for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { + iotable_init(cns3xxx_pcie[i].cfg_bases, + ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases)); +- cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i)); +- cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i)); + cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); + cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); + pci_common_init(&cns3xxx_pcie[i].hw_pci); diff --git a/target/linux/cns3xxx/patches-3.8/035-add_io_spaces.patch b/target/linux/cns3xxx/patches-3.8/035-add_io_spaces.patch new file mode 100644 index 0000000000..b4b018b089 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/035-add_io_spaces.patch @@ -0,0 +1,19 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -58,6 +58,16 @@ static struct map_desc cns3xxx_io_desc[] + .pfn = __phys_to_pfn(CNS3XXX_PM_BASE), + .length = SZ_4K, + .type = MT_DEVICE, ++ }, { ++ .virtual = CNS3XXX_SWITCH_BASE_VIRT, ++ .pfn = __phys_to_pfn(CNS3XXX_SWITCH_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = CNS3XXX_SSP_BASE_VIRT, ++ .pfn = __phys_to_pfn(CNS3XXX_SSP_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE, + }, + }; + diff --git a/target/linux/cns3xxx/patches-3.8/040-fiq_support.patch b/target/linux/cns3xxx/patches-3.8/040-fiq_support.patch new file mode 100644 index 0000000000..9c662a5cd1 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/040-fiq_support.patch @@ -0,0 +1,77 @@ +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -368,6 +368,7 @@ config ARCH_CNS3XXX + select CLKDEV_LOOKUP + select CPU_CACHE_FORCE_MULTI + select HAVE_SMP ++ select FIQ + help + Support for Cavium Networks CNS3XXX platform. + +--- a/arch/arm/kernel/fiq.c ++++ b/arch/arm/kernel/fiq.c +@@ -49,6 +49,8 @@ + + static unsigned long no_fiq_insn; + ++unsigned int fiq_number[2] = {0, 0}; ++ + /* Default reacquire function + * - we always relinquish FIQ control + * - we always reacquire FIQ control +@@ -70,9 +72,12 @@ static struct fiq_handler *current_fiq = + + int show_fiq_list(struct seq_file *p, int prec) + { +- if (current_fiq != &default_owner) +- seq_printf(p, "%*s: %s\n", prec, "FIQ", +- current_fiq->name); ++ if (current_fiq != &default_owner) { ++ seq_printf(p, "%*s: ", prec, "FIQ"); ++ seq_printf(p, "%10u ", fiq_number[0]); ++ seq_printf(p, "%10u ", fiq_number[1]); ++ seq_printf(p, " %s\n", current_fiq->name); ++ } + + return 0; + } +--- a/arch/arm/mach-cns3xxx/Makefile ++++ b/arch/arm/mach-cns3xxx/Makefile +@@ -1,5 +1,5 @@ + obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o + obj-$(CONFIG_PCI) += pcie.o + obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o +-obj-$(CONFIG_SMP) += platsmp.o headsmp.o ++obj-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o + obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o +--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h ++++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +@@ -294,6 +294,7 @@ + #define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100) + #define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100) + ++#define MISC_FIQ_CPU(x) MISC_MEM_MAP(0xA58 - (x) * 0x4) + /* + * Power management and clock control + */ +--- a/arch/arm/mach-cns3xxx/include/mach/irqs.h ++++ b/arch/arm/mach-cns3xxx/include/mach/irqs.h +@@ -14,6 +14,7 @@ + #define IRQ_LOCALTIMER 29 + #define IRQ_LOCALWDOG 30 + #define IRQ_TC11MP_GIC_START 32 ++#define FIQ_START 0 + + #include <mach/cns3xxx.h> + +--- a/arch/arm/mm/Kconfig ++++ b/arch/arm/mm/Kconfig +@@ -773,7 +773,7 @@ config NEEDS_SYSCALL_FOR_CMPXCHG + + config DMA_CACHE_RWFO + bool "Enable read/write for ownership DMA cache maintenance" +- depends on CPU_V6K && SMP ++ depends on CPU_V6K && SMP && !ARCH_CNS3XXX + default y + help + The Snoop Control Unit on ARM11MPCore does not detect the diff --git a/target/linux/cns3xxx/patches-3.8/045-twd_base.patch b/target/linux/cns3xxx/patches-3.8/045-twd_base.patch new file mode 100644 index 0000000000..a9ad3ec482 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/045-twd_base.patch @@ -0,0 +1,36 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -19,6 +19,7 @@ + #include <asm/mach/time.h> + #include <asm/mach/irq.h> + #include <asm/hardware/gic.h> ++#include <asm/smp_twd.h> + #include <asm/hardware/cache-l2x0.h> + #include <mach/cns3xxx.h> + #include "core.h" +@@ -187,6 +188,17 @@ static struct irqaction cns3xxx_timer_ir + .handler = cns3xxx_timer_interrupt, + }; + ++static void __init cns3xxx_init_twd(void) ++{ ++#ifdef CONFIG_LOCAL_TIMERS ++ static DEFINE_TWD_LOCAL_TIMER(cns3xx_twd_local_timer, ++ CNS3XXX_TC11MP_TWD_BASE, ++ IRQ_LOCALTIMER); ++ ++ twd_local_timer_register(&cns3xx_twd_local_timer); ++#endif ++} ++ + /* + * Set up the clock source and clock events devices + */ +@@ -240,6 +252,7 @@ static void __init __cns3xxx_timer_init( + setup_irq(timer_irq, &cns3xxx_timer_irq); + + cns3xxx_clockevents_init(timer_irq); ++ cns3xxx_init_twd(); + } + + static void __init cns3xxx_timer_init(void) diff --git a/target/linux/cns3xxx/patches-3.8/055-pcie_io.patch b/target/linux/cns3xxx/patches-3.8/055-pcie_io.patch new file mode 100644 index 0000000000..08a68f9d9d --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/055-pcie_io.patch @@ -0,0 +1,19 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -69,6 +69,16 @@ static struct map_desc cns3xxx_io_desc[] + .pfn = __phys_to_pfn(CNS3XXX_SSP_BASE), + .length = SZ_4K, + .type = MT_DEVICE, ++ }, { ++ .virtual = CNS3XXX_PCIE0_IO_BASE_VIRT, ++ .pfn = __phys_to_pfn(CNS3XXX_PCIE0_IO_BASE), ++ .length = SZ_16M, ++ .type = MT_DEVICE, ++ }, { ++ .virtual = CNS3XXX_PCIE1_IO_BASE_VIRT, ++ .pfn = __phys_to_pfn(CNS3XXX_PCIE1_IO_BASE), ++ .length = SZ_16M, ++ .type = MT_DEVICE, + }, + }; + diff --git a/target/linux/cns3xxx/patches-3.8/060-pcie_abort.patch b/target/linux/cns3xxx/patches-3.8/060-pcie_abort.patch new file mode 100644 index 0000000000..e1edf05877 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/060-pcie_abort.patch @@ -0,0 +1,129 @@ +--- a/arch/arm/mach-cns3xxx/pcie.c ++++ b/arch/arm/mach-cns3xxx/pcie.c +@@ -92,6 +92,79 @@ static void __iomem *cns3xxx_pci_cfg_bas + return base + offset; + } + ++static inline int check_master_abort(struct pci_bus *bus, unsigned int devfn, int where) ++{ ++ struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus); ++ ++ /* check PCI-compatible status register after access */ ++ if (cnspci->linked) { ++ void __iomem *host_base; ++ u32 sreg, ereg; ++ ++ host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual; ++ sreg = __raw_readw(host_base + 0x6) & 0xF900; ++ ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg ++ ++ if (sreg | ereg) { ++ /* SREG: ++ * BIT15 - Detected Parity Error ++ * BIT14 - Signaled System Error ++ * BIT13 - Received Master Abort ++ * BIT12 - Received Target Abort ++ * BIT11 - Signaled Target Abort ++ * BIT08 - Master Data Parity Error ++ * ++ * EREG: ++ * BIT20 - Unsupported Request ++ * BIT19 - ECRC ++ * BIT18 - Malformed TLP ++ * BIT17 - Receiver Overflow ++ * BIT16 - Unexpected Completion ++ * BIT15 - Completer Abort ++ * BIT14 - Completion Timeout ++ * BIT13 - Flow Control Protocol Error ++ * BIT12 - Poisoned TLP ++ * BIT04 - Data Link Protocol Error ++ * ++ * TODO: see Documentation/pci-error-recovery.txt ++ * implement error_detected handler ++ */ ++/* ++ printk("pci error: %04d:%02x:%02x.%02x sreg=0x%04x ereg=0x%08x", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), sreg, ereg); ++ if (sreg & BIT(15)) printk(" <PERR"); ++ if (sreg & BIT(14)) printk(" >SERR"); ++ if (sreg & BIT(13)) printk(" <MABRT"); ++ if (sreg & BIT(12)) printk(" <TABRT"); ++ if (sreg & BIT(11)) printk(" >TABRT"); ++ if (sreg & BIT( 8)) printk(" MPERR"); ++ ++ if (ereg & BIT(20)) printk(" Unsup"); ++ if (ereg & BIT(19)) printk(" ECRC"); ++ if (ereg & BIT(18)) printk(" MTLP"); ++ if (ereg & BIT(17)) printk(" OFLOW"); ++ if (ereg & BIT(16)) printk(" Unex"); ++ if (ereg & BIT(15)) printk(" ABRT"); ++ if (ereg & BIT(14)) printk(" COMPTO"); ++ if (ereg & BIT(13)) printk(" FLOW"); ++ if (ereg & BIT(12)) printk(" PTLP"); ++ if (ereg & BIT( 4)) printk(" DLINK"); ++ printk("\n"); ++*/ ++ pr_debug("%s failed port%d sreg=0x%04x\n", __func__, ++ cnspci->hw_pci.domain, sreg); ++ ++ /* make sure the status bits are reset */ ++ __raw_writew(sreg, host_base + 6); ++ __raw_writel(ereg, host_base + 0x104); ++ return 1; ++ } ++ } ++ else ++ return 1; ++ ++ return 0; ++} ++ + static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) + { +@@ -108,6 +181,11 @@ static int cns3xxx_pci_read_config(struc + + v = __raw_readl(base); + ++ if (check_master_abort(bus, devfn, where)) { ++ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)= master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ } ++ + if (bus->number == 0 && devfn == 0 && + (where & 0xffc) == PCI_CLASS_REVISION) { + /* +@@ -137,11 +215,19 @@ static int cns3xxx_pci_write_config(stru + return PCIBIOS_SUCCESSFUL; + + v = __raw_readl(base); ++ if (check_master_abort(bus, devfn, where)) { ++ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)=0x%08x master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val); ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ } + + v &= ~(mask << shift); + v |= (val & mask) << shift; + + __raw_writel(v, base); ++ if (check_master_abort(bus, devfn, where)) { ++ printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)=0x%08x master_abort on write\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val); ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ } + + return PCIBIOS_SUCCESSFUL; + } +@@ -352,8 +438,14 @@ static void __init cns3xxx_pcie_hw_init( + static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr, + struct pt_regs *regs) + { ++#if 0 ++/* R14_ABORT = PC+4 for XSCALE but not ARM11MPCORE ++ * ignore imprecise aborts and use PCI-compatible Status register to ++ * determine errors instead ++ */ + if (fsr & (1 << 10)) + regs->ARM_pc += 4; ++#endif + return 0; + } + diff --git a/target/linux/cns3xxx/patches-3.8/065-pcie_early_init.patch b/target/linux/cns3xxx/patches-3.8/065-pcie_early_init.patch new file mode 100644 index 0000000000..36e49812a0 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/065-pcie_early_init.patch @@ -0,0 +1,85 @@ +--- a/arch/arm/mach-cns3xxx/cns3420vb.c ++++ b/arch/arm/mach-cns3xxx/cns3420vb.c +@@ -263,11 +263,21 @@ static struct map_desc cns3420_io_desc[] + static void __init cns3420_map_io(void) + { + cns3xxx_map_io(); ++ cns3xxx_pcie_iotable_init(); + iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc)); + + cns3420_early_serial_setup(); + } + ++static int __init cns3420vb_pcie_init(void) ++{ ++ if (!machine_is_cns3420vb()) ++ return 0; ++ ++ return cns3xxx_pcie_init(); ++} ++subsys_initcall(cns3420vb_pcie_init); ++ + MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") + .atag_offset = 0x100, + .map_io = cns3420_map_io, +--- a/arch/arm/mach-cns3xxx/core.h ++++ b/arch/arm/mach-cns3xxx/core.h +@@ -13,6 +13,8 @@ + + extern struct smp_operations cns3xxx_smp_ops; + extern struct sys_timer cns3xxx_timer; ++extern void cns3xxx_pcie_iotable_init(void); ++ + + #ifdef CONFIG_CACHE_L2X0 + void __init cns3xxx_l2x0_init(void); +@@ -22,6 +24,7 @@ static inline void cns3xxx_l2x0_init(voi + + void __init cns3xxx_map_io(void); + void __init cns3xxx_init_irq(void); ++int __init cns3xxx_pcie_init(void); + void cns3xxx_power_off(void); + void cns3xxx_restart(char, const char *); + +--- a/arch/arm/mach-cns3xxx/pcie.c ++++ b/arch/arm/mach-cns3xxx/pcie.c +@@ -449,7 +449,18 @@ static int cns3xxx_pcie_abort_handler(un + return 0; + } + +-static int __init cns3xxx_pcie_init(void) ++ ++void __init cns3xxx_pcie_iotable_init() ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { ++ iotable_init(cns3xxx_pcie[i].cfg_bases, ++ ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases)); ++ } ++} ++ ++int __init cns3xxx_pcie_init(void) + { + int i; + +@@ -460,15 +471,14 @@ static int __init cns3xxx_pcie_init(void + "imprecise external abort"); + + for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { +- iotable_init(cns3xxx_pcie[i].cfg_bases, +- ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases)); + cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); +- cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); +- pci_common_init(&cns3xxx_pcie[i].hw_pci); ++ if (cns3xxx_pcie[i].linked) { ++ cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); ++ pci_common_init(&cns3xxx_pcie[i].hw_pci); ++ } + } + + pci_assign_unassigned_resources(); + + return 0; + } +-device_initcall(cns3xxx_pcie_init); diff --git a/target/linux/cns3xxx/patches-3.8/070-i2c_support.patch b/target/linux/cns3xxx/patches-3.8/070-i2c_support.patch new file mode 100644 index 0000000000..bdb19d6c84 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/070-i2c_support.patch @@ -0,0 +1,31 @@ +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -347,6 +347,18 @@ config I2C_CBUS_GPIO + This driver can also be built as a module. If so, the module + will be called i2c-cbus-gpio. + ++config I2C_CNS3XXX ++ tristate "Cavium CNS3xxx I2C driver" ++ depends on ARCH_CNS3XXX ++ help ++ Support for Cavium CNS3xxx I2C controller driver. ++ ++ This driver can also be built as a module. If so, the module ++ will be called i2c-cns3xxx. ++ ++ Please note that this driver might be needed to bring up other ++ devices such as Cavium CNS3xxx Ethernet. ++ + config I2C_CPM + tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)" + depends on (CPM1 || CPM2) && OF_I2C +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -87,6 +87,7 @@ obj-$(CONFIG_I2C_ACORN) += i2c-acorn.o + obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o + obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o + obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o ++obj-$(CONFIG_I2C_CNS3XXX) += i2c-cns3xxx.o + obj-$(CONFIG_SCx200_ACB) += scx200_acb.o + obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o + diff --git a/target/linux/cns3xxx/patches-3.8/075-spi_support.patch b/target/linux/cns3xxx/patches-3.8/075-spi_support.patch new file mode 100644 index 0000000000..1106472517 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/075-spi_support.patch @@ -0,0 +1,57 @@ +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -130,6 +130,13 @@ config SPI_CLPS711X + This enables dedicated general purpose SPI/Microwire1-compatible + master mode interface (SSI1) for CLPS711X-based CPUs. + ++config SPI_CNS3XXX ++ tristate "CNS3XXX SPI controller" ++ depends on ARCH_CNS3XXX && SPI_MASTER ++ select SPI_BITBANG ++ help ++ This enables using the CNS3XXX SPI controller in master mode. ++ + config SPI_COLDFIRE_QSPI + tristate "Freescale Coldfire QSPI controller" + depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x) +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -19,6 +19,7 @@ obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5x + obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o + obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o + obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o ++obj-$(CONFIG_SPI_CNS3XXX) += spi-cns3xxx.o + obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o + obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o + obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o +--- a/drivers/spi/spi-bitbang.c ++++ b/drivers/spi/spi-bitbang.c +@@ -328,6 +328,12 @@ static void bitbang_work(struct work_str + */ + if (!m->is_dma_mapped) + t->rx_dma = t->tx_dma = 0; ++ ++ if (t->transfer_list.next == &m->transfers) ++ t->last_in_message_list = 1; ++ else ++ t->last_in_message_list = 0; ++ + status = bitbang->txrx_bufs(spi, t); + } + if (status > 0) +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -511,6 +511,13 @@ struct spi_transfer { + u32 speed_hz; + + struct list_head transfer_list; ++ ++#ifdef CONFIG_ARCH_CNS3XXX ++ unsigned last_in_message_list; ++#ifdef CONFIG_SPI_CNS3XXX_2IOREAD ++ u8 dio_read; ++#endif ++#endif + }; + + /** diff --git a/target/linux/cns3xxx/patches-3.8/080-sata_support.patch b/target/linux/cns3xxx/patches-3.8/080-sata_support.patch new file mode 100644 index 0000000000..a4feb2c332 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/080-sata_support.patch @@ -0,0 +1,44 @@ +--- a/arch/arm/mach-cns3xxx/devices.c ++++ b/arch/arm/mach-cns3xxx/devices.c +@@ -41,7 +41,7 @@ static struct resource cns3xxx_ahci_reso + static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32); + + static struct platform_device cns3xxx_ahci_pdev = { +- .name = "ahci", ++ .name = "cns3xxx-ahci", + .id = 0, + .resource = cns3xxx_ahci_resource, + .num_resources = ARRAY_SIZE(cns3xxx_ahci_resource), +--- a/drivers/ata/ahci_platform.c ++++ b/drivers/ata/ahci_platform.c +@@ -31,6 +31,7 @@ enum ahci_type { + AHCI, /* standard platform ahci */ + IMX53_AHCI, /* ahci on i.mx53 */ + STRICT_AHCI, /* delayed DMA engine start */ ++ CNS3XXX_AHCI, /* AHCI on cns3xxx */ + }; + + static struct platform_device_id ahci_devtype[] = { +@@ -44,6 +45,9 @@ static struct platform_device_id ahci_de + .name = "strict-ahci", + .driver_data = STRICT_AHCI, + }, { ++ .name = "cns3xxx-ahci", ++ .driver_data = CNS3XXX_AHCI, ++ }, { + /* sentinel */ + } + }; +@@ -80,6 +84,12 @@ static const struct ata_port_info ahci_p + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_platform_ops, + }, ++ [CNS3XXX_AHCI] = { ++ .flags = AHCI_FLAG_COMMON, ++ .pio_mask = ATA_PIO4, ++ .udma_mask = ATA_UDMA6, ++ .port_ops = &ahci_platform_retry_srst_ops, ++ } + }; + + static struct scsi_host_template ahci_platform_sht = { diff --git a/target/linux/cns3xxx/patches-3.8/085-ethernet_support.patch b/target/linux/cns3xxx/patches-3.8/085-ethernet_support.patch new file mode 100644 index 0000000000..84548a322c --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/085-ethernet_support.patch @@ -0,0 +1,20 @@ +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -32,6 +32,7 @@ source "drivers/net/ethernet/calxeda/Kco + source "drivers/net/ethernet/chelsio/Kconfig" + source "drivers/net/ethernet/cirrus/Kconfig" + source "drivers/net/ethernet/cisco/Kconfig" ++source "drivers/net/ethernet/cavium/Kconfig" + source "drivers/net/ethernet/davicom/Kconfig" + + config DNET +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -15,6 +15,7 @@ obj-$(CONFIG_NET_BFIN) += adi/ + obj-$(CONFIG_NET_VENDOR_BROADCOM) += broadcom/ + obj-$(CONFIG_NET_VENDOR_BROCADE) += brocade/ + obj-$(CONFIG_NET_CALXEDA_XGMAC) += calxeda/ ++obj-$(CONFIG_NET_VENDOR_CAVIUM) += cavium/ + obj-$(CONFIG_NET_VENDOR_CHELSIO) += chelsio/ + obj-$(CONFIG_NET_VENDOR_CIRRUS) += cirrus/ + obj-$(CONFIG_NET_VENDOR_CISCO) += cisco/ diff --git a/target/linux/cns3xxx/patches-3.8/090-timers.patch b/target/linux/cns3xxx/patches-3.8/090-timers.patch new file mode 100644 index 0000000000..488539f727 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/090-timers.patch @@ -0,0 +1,109 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -122,12 +122,13 @@ static void cns3xxx_timer_set_mode(enum + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: +- reload = pclk * 20 / (3 * HZ) * 0x25000; ++ reload = pclk * 1000000 / HZ; + writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); + ctrl |= (1 << 0) | (1 << 2) | (1 << 9); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* period set, and timer enabled in 'next_event' hook */ ++ writel(0, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); + ctrl |= (1 << 2) | (1 << 9); + break; + case CLOCK_EVT_MODE_UNUSED: +@@ -152,11 +153,11 @@ static int cns3xxx_timer_set_next_event( + + static struct clock_event_device cns3xxx_tmr1_clockevent = { + .name = "cns3xxx timer1", +- .shift = 8, ++ .shift = 32, + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = cns3xxx_timer_set_mode, + .set_next_event = cns3xxx_timer_set_next_event, +- .rating = 350, ++ .rating = 300, + .cpumask = cpu_all_mask, + }; + +@@ -209,6 +210,35 @@ static void __init cns3xxx_init_twd(void + #endif + } + ++static cycle_t cns3xxx_get_cycles(struct clocksource *cs) ++{ ++ u64 val; ++ ++ val = readl(cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); ++ val &= 0xffff; ++ ++ return ((val << 32) | readl(cns3xxx_tmr1 + TIMER_FREERUN_OFFSET)); ++} ++ ++static struct clocksource clocksource_cns3xxx = { ++ .name = "freerun", ++ .rating = 200, ++ .read = cns3xxx_get_cycles, ++ .mask = CLOCKSOURCE_MASK(48), ++ .shift = 16, ++ .flags = CLOCK_SOURCE_IS_CONTINUOUS, ++}; ++ ++static void __init cns3xxx_clocksource_init(void) ++{ ++ /* Reset the FreeRunning counter */ ++ writel((1 << 16), cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); ++ ++ clocksource_cns3xxx.mult = ++ clocksource_khz2mult(100, clocksource_cns3xxx.shift); ++ clocksource_register(&clocksource_cns3xxx); ++} ++ + /* + * Set up the clock source and clock events devices + */ +@@ -226,13 +256,12 @@ static void __init __cns3xxx_timer_init( + /* stop free running timer3 */ + writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); + +- /* timer1 */ +- writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); +- writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); +- + writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET); + writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET); + ++ val = (cns3xxx_cpu_clock() >> 3) * 1000000 / HZ; ++ writel(val, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); ++ + /* mask irq, non-mask timer1 overflow */ + irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); + irq_mask &= ~(1 << 2); +@@ -244,23 +273,9 @@ static void __init __cns3xxx_timer_init( + val |= (1 << 9); + writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); + +- /* timer2 */ +- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET); +- writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET); +- +- /* mask irq */ +- irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); +- irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5)); +- writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); +- +- /* down counter */ +- val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); +- val |= (1 << 10); +- writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); +- +- /* Make irqs happen for the system timer */ + setup_irq(timer_irq, &cns3xxx_timer_irq); + ++ cns3xxx_clocksource_init(); + cns3xxx_clockevents_init(timer_irq); + cns3xxx_init_twd(); + } diff --git a/target/linux/cns3xxx/patches-3.8/095-gpio_support.patch b/target/linux/cns3xxx/patches-3.8/095-gpio_support.patch new file mode 100644 index 0000000000..8f8f26131a --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/095-gpio_support.patch @@ -0,0 +1,74 @@ +--- a/arch/arm/mach-cns3xxx/cns3420vb.c ++++ b/arch/arm/mach-cns3xxx/cns3420vb.c +@@ -247,6 +247,10 @@ static void __init cns3420_init(void) + + cns3xxx_ahci_init(); + cns3xxx_sdhci_init(); ++ cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA, ++ NR_IRQS_CNS3XXX); ++ cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB, ++ NR_IRQS_CNS3XXX + 32); + + pm_power_off = cns3xxx_power_off; + } +@@ -262,7 +266,7 @@ static struct map_desc cns3420_io_desc[] + + static void __init cns3420_map_io(void) + { +- cns3xxx_map_io(); ++ cns3xxx_common_init(); + cns3xxx_pcie_iotable_init(); + iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc)); + +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -82,7 +82,7 @@ static struct map_desc cns3xxx_io_desc[] + }, + }; + +-void __init cns3xxx_map_io(void) ++void __init cns3xxx_common_init(void) + { + iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc)); + } +--- a/arch/arm/mach-cns3xxx/core.h ++++ b/arch/arm/mach-cns3xxx/core.h +@@ -22,7 +22,7 @@ void __init cns3xxx_l2x0_init(void); + static inline void cns3xxx_l2x0_init(void) {} + #endif /* CONFIG_CACHE_L2X0 */ + +-void __init cns3xxx_map_io(void); ++void __init cns3xxx_common_init(void); + void __init cns3xxx_init_irq(void); + int __init cns3xxx_pcie_init(void); + void cns3xxx_power_off(void); +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -361,6 +361,8 @@ config ARCH_CNS3XXX + bool "Cavium Networks CNS3XXX family" + select ARM_GIC + select CPU_V6K ++ select ARCH_REQUIRE_GPIOLIB ++ select GENERIC_IRQ_CHIP + select GENERIC_CLOCKEVENTS + select MIGHT_HAVE_CACHE_L2X0 + select MIGHT_HAVE_PCI +--- a/arch/arm/mach-cns3xxx/Makefile ++++ b/arch/arm/mach-cns3xxx/Makefile +@@ -1,4 +1,4 @@ +-obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o ++obj-$(CONFIG_ARCH_CNS3XXX) += core.o gpio.o pm.o devices.o + obj-$(CONFIG_PCI) += pcie.o + obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o + obj-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o +--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h ++++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +@@ -627,7 +627,7 @@ int cns3xxx_cpu_clock(void); + + #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX) + #undef NR_IRQS +-#define NR_IRQS NR_IRQS_CNS3XXX ++#define NR_IRQS (NR_IRQS_CNS3XXX + 64) + #endif + + #endif /* __MACH_BOARD_CNS3XXX_H */ diff --git a/target/linux/cns3xxx/patches-3.8/097-l2x0_cmdline_disable.patch b/target/linux/cns3xxx/patches-3.8/097-l2x0_cmdline_disable.patch new file mode 100644 index 0000000000..eb5c8113c3 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/097-l2x0_cmdline_disable.patch @@ -0,0 +1,70 @@ +--- a/arch/arm/mach-cns3xxx/core.c ++++ b/arch/arm/mach-cns3xxx/core.c +@@ -293,13 +293,26 @@ struct sys_timer cns3xxx_timer = { + + #ifdef CONFIG_CACHE_L2X0 + +-void __init cns3xxx_l2x0_init(void) ++static int cns3xxx_l2x0_enable = 1; ++ ++static int __init cns3xxx_l2x0_disable(char *s) ++{ ++ cns3xxx_l2x0_enable = 0; ++ return 1; ++} ++__setup("nol2x0", cns3xxx_l2x0_disable); ++ ++static int __init cns3xxx_l2x0_init(void) + { +- void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); ++ void __iomem *base; + u32 val; + ++ if (!cns3xxx_l2x0_enable) ++ return 0; ++ ++ base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); + if (WARN_ON(!base)) +- return; ++ return 0; + + /* + * Tag RAM Control register +@@ -329,7 +342,10 @@ void __init cns3xxx_l2x0_init(void) + + /* 32 KiB, 8-way, parity disable */ + l2x0_init(base, 0x00540000, 0xfe000fff); ++ ++ return 0; + } ++arch_initcall(cns3xxx_l2x0_init); + + #endif /* CONFIG_CACHE_L2X0 */ + +--- a/arch/arm/mach-cns3xxx/cns3420vb.c ++++ b/arch/arm/mach-cns3xxx/cns3420vb.c +@@ -241,8 +241,6 @@ static struct platform_device *cns3420_p + + static void __init cns3420_init(void) + { +- cns3xxx_l2x0_init(); +- + platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); + + cns3xxx_ahci_init(); +--- a/arch/arm/mach-cns3xxx/core.h ++++ b/arch/arm/mach-cns3xxx/core.h +@@ -15,13 +15,6 @@ extern struct smp_operations cns3xxx_smp + extern struct sys_timer cns3xxx_timer; + extern void cns3xxx_pcie_iotable_init(void); + +- +-#ifdef CONFIG_CACHE_L2X0 +-void __init cns3xxx_l2x0_init(void); +-#else +-static inline void cns3xxx_l2x0_init(void) {} +-#endif /* CONFIG_CACHE_L2X0 */ +- + void __init cns3xxx_common_init(void); + void __init cns3xxx_init_irq(void); + int __init cns3xxx_pcie_init(void); diff --git a/target/linux/cns3xxx/patches-3.8/200-dwc_otg_support.patch b/target/linux/cns3xxx/patches-3.8/200-dwc_otg_support.patch new file mode 100644 index 0000000000..8d4d79e6d3 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/200-dwc_otg_support.patch @@ -0,0 +1,48 @@ +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -81,6 +81,7 @@ obj-$(CONFIG_PARIDE) += block/paride/ + obj-$(CONFIG_TC) += tc/ + obj-$(CONFIG_UWB) += uwb/ + obj-$(CONFIG_USB_OTG_UTILS) += usb/ ++obj-$(CONFIG_USB_DWC_OTG) += usb/dwc/ + obj-$(CONFIG_USB) += usb/ + obj-$(CONFIG_PCI) += usb/ + obj-$(CONFIG_USB_GADGET) += usb/ +--- a/drivers/usb/Kconfig ++++ b/drivers/usb/Kconfig +@@ -138,6 +138,8 @@ source "drivers/usb/chipidea/Kconfig" + + source "drivers/usb/renesas_usbhs/Kconfig" + ++source "drivers/usb/dwc/Kconfig" ++ + source "drivers/usb/class/Kconfig" + + source "drivers/usb/storage/Kconfig" +--- a/drivers/usb/core/urb.c ++++ b/drivers/usb/core/urb.c +@@ -17,7 +17,11 @@ static void urb_destroy(struct kref *kre + + if (urb->transfer_flags & URB_FREE_BUFFER) + kfree(urb->transfer_buffer); +- ++ if (urb->aligned_transfer_buffer) { ++ kfree(urb->aligned_transfer_buffer); ++ urb->aligned_transfer_buffer = 0; ++ urb->aligned_transfer_dma = 0; ++ } + kfree(urb); + } + +--- a/include/linux/usb.h ++++ b/include/linux/usb.h +@@ -1401,6 +1401,9 @@ struct urb { + unsigned int transfer_flags; /* (in) URB_SHORT_NOT_OK | ...*/ + void *transfer_buffer; /* (in) associated data buffer */ + dma_addr_t transfer_dma; /* (in) dma addr for transfer_buffer */ ++ void *aligned_transfer_buffer; /* (in) associeated data buffer */ ++ dma_addr_t aligned_transfer_dma;/* (in) dma addr for transfer_buffer */ ++ u32 aligned_transfer_buffer_length; /* (in) data buffer length */ + struct scatterlist *sg; /* (in) scatter gather buffer list */ + int num_mapped_sgs; /* (internal) mapped sg entries */ + int num_sgs; /* (in) number of entries in the sg list */ diff --git a/target/linux/cns3xxx/patches-3.8/300-laguna_support.patch b/target/linux/cns3xxx/patches-3.8/300-laguna_support.patch new file mode 100644 index 0000000000..210ab023f3 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/300-laguna_support.patch @@ -0,0 +1,47 @@ +--- a/arch/arm/mach-cns3xxx/Kconfig ++++ b/arch/arm/mach-cns3xxx/Kconfig +@@ -9,4 +9,12 @@ config MACH_CNS3420VB + This is a platform with an on-board ARM11 MPCore and has support + for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc. + ++config MACH_GW2388 ++ bool "Support for Gateworks Laguna Platform" ++ help ++ Include support for the Gateworks Laguna Platform ++ ++ This is a platform with an on-board ARM11 MPCore and has support ++ for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc. ++ + endmenu +--- a/arch/arm/mach-cns3xxx/Makefile ++++ b/arch/arm/mach-cns3xxx/Makefile +@@ -1,5 +1,6 @@ + obj-$(CONFIG_ARCH_CNS3XXX) += core.o gpio.o pm.o devices.o + obj-$(CONFIG_PCI) += pcie.o + obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o ++obj-$(CONFIG_MACH_GW2388) += laguna.o + obj-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o + obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o +--- a/arch/arm/mach-cns3xxx/devices.c ++++ b/arch/arm/mach-cns3xxx/devices.c +@@ -19,6 +19,7 @@ + #include <mach/cns3xxx.h> + #include <mach/irqs.h> + #include <mach/pm.h> ++#include <asm/mach-types.h> + #include "core.h" + #include "devices.h" + +@@ -102,7 +103,11 @@ void __init cns3xxx_sdhci_init(void) + u32 gpioa_pins = __raw_readl(gpioa); + + /* MMC/SD pins share with GPIOA */ +- gpioa_pins |= 0x1fff0004; ++ if (machine_is_gw2388()) { ++ gpioa_pins |= 0x1fff0000; ++ } else { ++ gpioa_pins |= 0x1fff0004; ++ } + __raw_writel(gpioa_pins, gpioa); + + cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); diff --git a/target/linux/cns3xxx/patches-3.8/305-laguna_sdhci_card_detect.patch b/target/linux/cns3xxx/patches-3.8/305-laguna_sdhci_card_detect.patch new file mode 100644 index 0000000000..03b2bb7aa0 --- /dev/null +++ b/target/linux/cns3xxx/patches-3.8/305-laguna_sdhci_card_detect.patch @@ -0,0 +1,16 @@ +--- a/drivers/mmc/host/sdhci-cns3xxx.c ++++ b/drivers/mmc/host/sdhci-cns3xxx.c +@@ -89,10 +89,11 @@ static struct sdhci_pltfm_data sdhci_cns + .ops = &sdhci_cns3xxx_ops, + .quirks = SDHCI_QUIRK_BROKEN_DMA | + SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | +- SDHCI_QUIRK_INVERTED_WRITE_PROTECT | ++ //SDHCI_QUIRK_INVERTED_WRITE_PROTECT | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | +- SDHCI_QUIRK_NONSTANDARD_CLOCK, ++ SDHCI_QUIRK_NONSTANDARD_CLOCK | ++ SDHCI_QUIRK_BROKEN_CARD_DETECTION, + }; + + static int sdhci_cns3xxx_probe(struct platform_device *pdev) |