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| author | Jonas Gorski <jogo@openwrt.org> | 2014-12-01 00:51:51 +0000 |
|---|---|---|
| committer | Jonas Gorski <jogo@openwrt.org> | 2014-12-01 00:51:51 +0000 |
| commit | ef4f69adc0a42e81368c2e52c2f5cf12c4343101 (patch) | |
| tree | 58bdc9e09cce7b7c0de44295b9ce2e2e561dfa27 /target/linux/brcm63xx/patches-3.14/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch | |
| parent | bb312899f6b6c2a979f39e56f0ff8659b5a57a9b (diff) | |
| download | master-31e0f0ae-ef4f69adc0a42e81368c2e52c2f5cf12c4343101.tar.gz master-31e0f0ae-ef4f69adc0a42e81368c2e52c2f5cf12c4343101.tar.bz2 master-31e0f0ae-ef4f69adc0a42e81368c2e52c2f5cf12c4343101.zip | |
brcm63xx: convert to irq domain
Add irq-domain aware irqchip drivers for the irq controllers of bcm63xx
and switch to use them.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 43454
Diffstat (limited to 'target/linux/brcm63xx/patches-3.14/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch')
| -rw-r--r-- | target/linux/brcm63xx/patches-3.14/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/brcm63xx/patches-3.14/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch b/target/linux/brcm63xx/patches-3.14/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch index 5fe2078466..24a5888ef5 100644 --- a/target/linux/brcm63xx/patches-3.14/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch +++ b/target/linux/brcm63xx/patches-3.14/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch @@ -115,7 +115,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> return -ENODEV; --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h -@@ -707,6 +707,7 @@ +@@ -708,6 +708,7 @@ #define GPIO_STRAPBUS_REG 0x40 #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1) @@ -123,7 +123,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> #define STRAPBUS_6368_BOOT_SEL_MASK 0x3 #define STRAPBUS_6368_BOOT_SEL_NAND 0 #define STRAPBUS_6368_BOOT_SEL_SERIAL 1 -@@ -1577,6 +1578,7 @@ +@@ -1578,6 +1579,7 @@ #define IDDQ_CTRL_63268_USBH (1 << 4) #define MISC_STRAPBUS_6328_REG 0x240 |