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author | Jonas Gorski <jogo@openwrt.org> | 2013-07-20 11:30:26 +0000 |
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committer | Jonas Gorski <jogo@openwrt.org> | 2013-07-20 11:30:26 +0000 |
commit | 7ef37c8e3e5a787f91581fa78b527d78b5e0dc1c (patch) | |
tree | bb8f025c953044895a91e4ceedd9fed84c491554 /target/linux/brcm63xx/patches-3.10/317-MIPS-BCM63XX-use-a-helper-for-getting-the-right-regi.patch | |
parent | 205f7248aeb39ecd018b5cd883af2512787df505 (diff) | |
download | master-31e0f0ae-7ef37c8e3e5a787f91581fa78b527d78b5e0dc1c.tar.gz master-31e0f0ae-7ef37c8e3e5a787f91581fa78b527d78b5e0dc1c.tar.bz2 master-31e0f0ae-7ef37c8e3e5a787f91581fa78b527d78b5e0dc1c.zip |
brcm63xx: add linux 3.10 support
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 37481
Diffstat (limited to 'target/linux/brcm63xx/patches-3.10/317-MIPS-BCM63XX-use-a-helper-for-getting-the-right-regi.patch')
-rw-r--r-- | target/linux/brcm63xx/patches-3.10/317-MIPS-BCM63XX-use-a-helper-for-getting-the-right-regi.patch | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.10/317-MIPS-BCM63XX-use-a-helper-for-getting-the-right-regi.patch b/target/linux/brcm63xx/patches-3.10/317-MIPS-BCM63XX-use-a-helper-for-getting-the-right-regi.patch new file mode 100644 index 0000000000..e3377313f6 --- /dev/null +++ b/target/linux/brcm63xx/patches-3.10/317-MIPS-BCM63XX-use-a-helper-for-getting-the-right-regi.patch @@ -0,0 +1,80 @@ +From 353f07637d82cf485a9319d203a6ed9b38590526 Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Thu, 25 Apr 2013 15:35:12 +0200 +Subject: [PATCH 09/14] MIPS: BCM63XX: use a helper for getting the right + register address + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/irq.c | 30 ++++++++++++++++++++++++------ + 1 file changed, 24 insertions(+), 6 deletions(-) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -284,6 +284,20 @@ static inline u32 get_ext_irq_perf_reg(i + return ext_irq_cfg_reg2; + } + ++static inline u32 get_irq_stat_addr(int pin) ++{ ++ if (pin == 0) ++ return irq_stat_addr0; ++ return irq_stat_addr1; ++} ++ ++static inline u32 get_irq_mask_addr(int pin) ++{ ++ if (pin == 0) ++ return irq_mask_addr0; ++ return irq_mask_addr1; ++} ++ + static inline void handle_internal(int intbit) + { + if (is_ext_irq_cascaded && +@@ -307,13 +321,15 @@ void __dispatch_internal_##width(void) + unsigned int src, tgt; \ + bool irqs_pending = false; \ + static int i; \ ++ u32 irq_stat_addr = get_irq_stat_addr(0); \ ++ u32 irq_mask_addr = get_irq_mask_addr(0); \ + \ + /* read registers in reverse order */ \ + for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ + u32 val; \ + \ +- val = bcm_readl(irq_stat_addr0 + src * sizeof(u32)); \ +- val &= bcm_readl(irq_mask_addr0 + src * sizeof(u32)); \ ++ val = bcm_readl(irq_stat_addr + src * sizeof(u32)); \ ++ val &= bcm_readl(irq_mask_addr + src * sizeof(u32)); \ + pending[--tgt] = val; \ + \ + if (val) \ +@@ -339,10 +355,11 @@ static void __internal_irq_mask_##width( + u32 val; \ + unsigned reg = (irq / 32) ^ (width/32 - 1); \ + unsigned bit = irq & 0x1f; \ ++ u32 irq_mask_addr = get_irq_mask_addr(0); \ + \ +- val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32)); \ ++ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ + val &= ~(1 << bit); \ +- bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32)); \ ++ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ + } \ + \ + static void __internal_irq_unmask_##width(unsigned int irq) \ +@@ -350,10 +367,11 @@ static void __internal_irq_unmask_##widt + u32 val; \ + unsigned reg = (irq / 32) ^ (width/32 - 1); \ + unsigned bit = irq & 0x1f; \ ++ u32 irq_mask_addr = get_irq_mask_addr(0); \ + \ +- val = bcm_readl(irq_mask_addr0 + reg * sizeof(u32)); \ ++ val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \ + val |= (1 << bit); \ +- bcm_writel(val, irq_mask_addr0 + reg * sizeof(u32)); \ ++ bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \ + } + + BUILD_IPIC_INTERNAL(32); |