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| author | Hauke Mehrtens <hauke@hauke-m.de> | 2011-06-27 20:20:11 +0000 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2011-06-27 20:20:11 +0000 |
| commit | e439de144f0bd6dd3cdea921960bb5ae9a7be208 (patch) | |
| tree | d891aa27a5c8e6557e4dca0a35f3f7c28d6ab7b6 /target/linux/brcm47xx/patches-3.0/250-ssb_fix_ssb_clock_rate.patch | |
| parent | c1873c46b86fd0bc0d2bc4177209404f0a614097 (diff) | |
| download | master-31e0f0ae-e439de144f0bd6dd3cdea921960bb5ae9a7be208.tar.gz master-31e0f0ae-e439de144f0bd6dd3cdea921960bb5ae9a7be208.tar.bz2 master-31e0f0ae-e439de144f0bd6dd3cdea921960bb5ae9a7be208.zip | |
brcm47xx: fix Linux-3.0 and fix clock rate detection.
SVN-Revision: 27294
Diffstat (limited to 'target/linux/brcm47xx/patches-3.0/250-ssb_fix_ssb_clock_rate.patch')
| -rw-r--r-- | target/linux/brcm47xx/patches-3.0/250-ssb_fix_ssb_clock_rate.patch | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/target/linux/brcm47xx/patches-3.0/250-ssb_fix_ssb_clock_rate.patch b/target/linux/brcm47xx/patches-3.0/250-ssb_fix_ssb_clock_rate.patch new file mode 100644 index 0000000000..fe6507b8de --- /dev/null +++ b/target/linux/brcm47xx/patches-3.0/250-ssb_fix_ssb_clock_rate.patch @@ -0,0 +1,25 @@ +From 974353557959d8ec1c022511cd1b3eeaa7ed482a Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Sat, 4 Jun 2011 15:55:24 +0200 +Subject: [PATCH 15/15] ssb: fix ssb clock rate according to broadcom source + +This fix was done according to si_clock_rate function in broadcom siutils.c + +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + drivers/ssb/main.c | 4 ++-- + 1 files changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/ssb/main.c ++++ b/drivers/ssb/main.c +@@ -1002,8 +1002,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32 + switch (plltype) { + case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ + if (m & SSB_CHIPCO_CLK_T6_MMASK) +- return SSB_CHIPCO_CLK_T6_M0; +- return SSB_CHIPCO_CLK_T6_M1; ++ return SSB_CHIPCO_CLK_T6_M1; ++ return SSB_CHIPCO_CLK_T6_M0; + case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ + case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ + case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ |