diff options
author | Felix Fietkau <nbd@openwrt.org> | 2006-10-13 22:51:49 +0200 |
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committer | Felix Fietkau <nbd@openwrt.org> | 2016-03-20 17:29:15 +0100 |
commit | 60c1f0f64d23003a19a07d6b9638542130f6641d (patch) | |
tree | 8fb2787f4c49baded97cd55e0c371fe1cffce2b6 /target/linux/aruba-2.6/patches/003-pci.patch | |
parent | d58a09110ccfa95f06c983fe796806f2e035c9d2 (diff) | |
parent | b3ce218b51746d3a576221ea542facf3a1703ab2 (diff) | |
download | master-31e0f0ae-60c1f0f64d23003a19a07d6b9638542130f6641d.tar.gz master-31e0f0ae-60c1f0f64d23003a19a07d6b9638542130f6641d.tar.bz2 master-31e0f0ae-60c1f0f64d23003a19a07d6b9638542130f6641d.zip |
finally move buildroot-ng to trunk
Diffstat (limited to 'target/linux/aruba-2.6/patches/003-pci.patch')
-rw-r--r-- | target/linux/aruba-2.6/patches/003-pci.patch | 618 |
1 files changed, 618 insertions, 0 deletions
diff --git a/target/linux/aruba-2.6/patches/003-pci.patch b/target/linux/aruba-2.6/patches/003-pci.patch new file mode 100644 index 0000000000..0cad12a087 --- /dev/null +++ b/target/linux/aruba-2.6/patches/003-pci.patch @@ -0,0 +1,618 @@ +diff -Nur linux-2.6.15/arch/mips/pci/fixup-aruba.c linux-2.6.15-openwrt/arch/mips/pci/fixup-aruba.c +--- linux-2.6.15/arch/mips/pci/fixup-aruba.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.15-openwrt/arch/mips/pci/fixup-aruba.c 2006-01-10 00:34:41.000000000 +0100 +@@ -0,0 +1,115 @@ ++/************************************************************************** ++ * ++ * BRIEF MODULE DESCRIPTION ++ * PCI fixups for IDT EB434 board ++ * ++ * Copyright 2004 IDT Inc. (rischelp@idt.com) ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * ++ ************************************************************************** ++ * May 2004 rkt, neb ++ * ++ * Initial Release ++ * ++ * ++ * ++ ************************************************************************** ++ */ ++ ++#include <linux/config.h> ++#include <linux/types.h> ++#include <linux/pci.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <asm/idt-boards/rc32434/rc32434.h> ++#include <asm/idt-boards/rc32434/rc32434_pci.h> ++ ++int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ ++ if (dev->bus->number != 0) { ++ return 0; ++ } ++ ++ slot = PCI_SLOT(dev->devfn); ++ dev->irq = 0; ++ ++ if (slot > 0 && slot <= 15) { ++#if 1 ++ if(slot == 10) { ++ if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 9; // intA ++ } else if(slot == 11) { ++ if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 10; // intA ++ if(pin == 2) dev->irq = GROUP4_IRQ_BASE + 10; // intA ++ if(pin == 3) dev->irq = GROUP4_IRQ_BASE + 10; // intA ++ } else if(slot == 12) { ++ if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 11; // intA ++ if(pin == 2) dev->irq = GROUP4_IRQ_BASE + 12; // intB ++ } else if (slot == 13) { ++ if(pin == 1) dev->irq = GROUP4_IRQ_BASE + 12; // intA ++ if(pin == 2) dev->irq = GROUP4_IRQ_BASE + 11; // intB ++ } else { ++ dev->irq = GROUP4_IRQ_BASE + 11; ++ } ++#else ++ switch (pin) { ++ case 1: /* INTA*/ ++ dev->irq = GROUP4_IRQ_BASE + 11; ++ break; ++ case 2: /* INTB */ ++ dev->irq = GROUP4_IRQ_BASE + 11; ++ break; ++ case 3: /* INTC */ ++ dev->irq = GROUP4_IRQ_BASE + 11; ++ break; ++ case 4: /* INTD */ ++ dev->irq = GROUP4_IRQ_BASE + 11; ++ break; ++ default: ++ dev->irq = 0xff; ++ break; ++ } ++#endif ++#ifdef DEBUG ++ printk("irq fixup: slot %d, pin %d, irq %d\n", ++ slot, pin, dev->irq); ++#endif ++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE,dev->irq); ++ } ++ return (dev->irq); ++} ++ ++struct pci_fixup pcibios_fixups[] = { ++ {0} ++}; ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff -Nur linux-2.6.15/arch/mips/pci/Makefile linux-2.6.15-openwrt/arch/mips/pci/Makefile +--- linux-2.6.15/arch/mips/pci/Makefile 2006-01-03 04:21:10.000000000 +0100 ++++ linux-2.6.15-openwrt/arch/mips/pci/Makefile 2006-01-10 00:32:32.000000000 +0100 +@@ -56,3 +56,4 @@ + obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o + obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o + obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o ++obj-$(CONFIG_MACH_ARUBA) += fixup-aruba.o ops-aruba.o pci-aruba.o +diff -Nur linux-2.6.15/arch/mips/pci/ops-aruba.c linux-2.6.15-openwrt/arch/mips/pci/ops-aruba.c +--- linux-2.6.15/arch/mips/pci/ops-aruba.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.15-openwrt/arch/mips/pci/ops-aruba.c 2006-01-10 00:32:32.000000000 +0100 +@@ -0,0 +1,204 @@ ++/************************************************************************** ++ * ++ * BRIEF MODULE DESCRIPTION ++ * pci_ops for IDT EB434 board ++ * ++ * Copyright 2004 IDT Inc. (rischelp@idt.com) ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * ++ ************************************************************************** ++ * May 2004 rkt, neb ++ * ++ * Initial Release ++ * ++ * ++ * ++ ************************************************************************** ++ */ ++ ++#include <linux/config.h> ++#include <linux/init.h> ++#include <linux/pci.h> ++#include <linux/types.h> ++#include <linux/delay.h> ++ ++#include <asm/cpu.h> ++#include <asm/io.h> ++ ++#include <asm/idt-boards/rc32434/rc32434.h> ++#include <asm/idt-boards/rc32434/rc32434_pci.h> ++ ++#define PCI_ACCESS_READ 0 ++#define PCI_ACCESS_WRITE 1 ++ ++ ++#define PCI_CFG_SET(slot,func,off) \ ++ (rc32434_pci->pcicfga = (0x80000000 | ((slot)<<11) | \ ++ ((func)<<8) | (off))) ++ ++static int config_access(unsigned char access_type, struct pci_bus *bus, ++ unsigned int devfn, unsigned char where, ++ u32 * data) ++{ ++ /* ++ * config cycles are on 4 byte boundary only ++ */ ++ unsigned int slot = PCI_SLOT(devfn); ++ u8 func = PCI_FUNC(devfn); ++ ++ if (slot < 2 || slot > 15) { ++ *data = 0xFFFFFFFF; ++ return -1; ++ } ++ /* Setup address */ ++ PCI_CFG_SET(slot, func, where); ++ rc32434_sync(); ++ ++ if (access_type == PCI_ACCESS_WRITE) { ++ rc32434_sync(); ++ rc32434_pci->pcicfgd = *data; ++ } else { ++ rc32434_sync(); ++ *data = rc32434_pci->pcicfgd; ++ } ++ ++ rc32434_sync(); ++ ++ return 0; ++} ++ ++ ++/* ++ * We can't address 8 and 16 bit words directly. Instead we have to ++ * read/write a 32bit word and mask/modify the data we actually want. ++ */ ++static int read_config_byte(struct pci_bus *bus, unsigned int devfn, ++ int where, u8 * val) ++{ ++ u32 data; ++ int ret; ++ ++ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); ++ *val = (data >> ((where & 3) << 3)) & 0xff; ++ return ret; ++} ++ ++static int read_config_word(struct pci_bus *bus, unsigned int devfn, ++ int where, u16 * val) ++{ ++ u32 data; ++ int ret; ++ ++ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); ++ *val = (data >> ((where & 3) << 3)) & 0xffff; ++ return ret; ++} ++ ++static int read_config_dword(struct pci_bus *bus, unsigned int devfn, ++ int where, u32 * val) ++{ ++ int ret; ++ ++ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val); ++ return ret; ++} ++ ++static int ++write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, ++ u8 val) ++{ ++ u32 data = 0; ++ ++ if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) ++ return -1; ++ ++ data = (data & ~(0xff << ((where & 3) << 3))) | ++ (val << ((where & 3) << 3)); ++ ++ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) ++ return -1; ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++ ++static int ++write_config_word(struct pci_bus *bus, unsigned int devfn, int where, ++ u16 val) ++{ ++ u32 data = 0; ++ ++ if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) ++ return -1; ++ ++ data = (data & ~(0xffff << ((where & 3) << 3))) | ++ (val << ((where & 3) << 3)); ++ ++ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) ++ return -1; ++ ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++ ++static int ++write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, ++ u32 val) ++{ ++ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val)) ++ return -1; ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static int pci_config_read(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 * val) ++{ ++ switch (size) { ++ case 1: ++ return read_config_byte(bus, devfn, where, (u8 *) val); ++ case 2: ++ return read_config_word(bus, devfn, where, (u16 *) val); ++ default: ++ return read_config_dword(bus, devfn, where, val); ++ } ++} ++ ++static int pci_config_write(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 val) ++{ ++ switch (size) { ++ case 1: ++ return write_config_byte(bus, devfn, where, (u8) val); ++ case 2: ++ return write_config_word(bus, devfn, where, (u16) val); ++ default: ++ return write_config_dword(bus, devfn, where, val); ++ } ++} ++ ++struct pci_ops rc32434_pci_ops = { ++ .read = pci_config_read, ++ .write = pci_config_write, ++}; +diff -Nur linux-2.6.15/arch/mips/pci/pci-aruba.c linux-2.6.15-openwrt/arch/mips/pci/pci-aruba.c +--- linux-2.6.15/arch/mips/pci/pci-aruba.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.15-openwrt/arch/mips/pci/pci-aruba.c 2006-01-10 00:32:32.000000000 +0100 +@@ -0,0 +1,235 @@ ++/************************************************************************** ++ * ++ * BRIEF MODULE DESCRIPTION ++ * PCI initialization for IDT EB434 board ++ * ++ * Copyright 2004 IDT Inc. (rischelp@idt.com) ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * ++ ************************************************************************** ++ * May 2004 rkt, neb ++ * ++ * Initial Release ++ * ++ * ++ * ++ ************************************************************************** ++ */ ++ ++#include <linux/config.h> ++#include <linux/types.h> ++#include <linux/pci.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <asm/idt-boards/rc32434/rc32434.h> ++#include <asm/idt-boards/rc32434/rc32434_pci.h> ++ ++#define PCI_ACCESS_READ 0 ++#define PCI_ACCESS_WRITE 1 ++ ++#undef DEBUG ++#ifdef DEBUG ++#define DBG(x...) printk(x) ++#else ++#define DBG(x...) ++#endif ++/* define an unsigned array for the PCI registers */ ++unsigned int korinaCnfgRegs[25] = { ++ KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4, ++ KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8, ++ KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12, ++ KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16, ++ KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20, ++ KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24 ++}; ++ ++static struct resource rc32434_res_pci_mem2; ++ ++static struct resource rc32434_res_pci_mem1 = { ++ .name = "PCI MEM1", ++ .start = 0x50000000, ++ .end = 0x5FFFFFFF, ++ .flags = IORESOURCE_MEM, ++ .child = &rc32434_res_pci_mem2, ++}; ++static struct resource rc32434_res_pci_mem2 = { ++ .name = "PCI MEM2", ++ .start = 0x60000000, ++ .end = 0x6FFFFFFF, ++ .flags = IORESOURCE_MEM, ++ .parent = &rc32434_res_pci_mem1, ++}; ++static struct resource rc32434_res_pci_io1 = { ++ .name = "PCI I/O1", ++ .start = 0x18800000, ++ .end = 0x188FFFFF, ++ .flags = IORESOURCE_IO, ++}; ++ ++extern struct pci_ops rc32434_pci_ops; ++ ++struct pci_controller rc32434_controller = { ++ .pci_ops = &rc32434_pci_ops, ++ .mem_resource = &rc32434_res_pci_mem1, ++ .io_resource = &rc32434_res_pci_io1, ++ .mem_offset = 0x00000000UL, ++ .io_offset = 0x00000000UL, ++}; ++ ++extern unsigned int arch_has_pci; ++ ++static int __init rc32434_pcibridge_init(void) ++{ ++ ++ unsigned int pciConfigAddr = 0;/*used for writing pci config values */ ++ int loopCount=0 ;/*used for the loop */ ++ ++ unsigned int pcicValue, pcicData=0; ++ unsigned int dummyRead, pciCntlVal = 0; ++ ++ if (!arch_has_pci) return 0; ++ ++ printk("PCI: Initializing PCI\n"); ++ ++ /* Disable the IP bus error for PCI scaning */ ++ pciCntlVal=rc32434_pci->pcic; ++ pciCntlVal &= 0xFFFFFF7; ++ rc32434_pci->pcic = pciCntlVal; ++ ++ ioport_resource.start = rc32434_res_pci_io1.start; ++ ioport_resource.end = rc32434_res_pci_io1.end; ++/* ++ iomem_resource.start = rc32434_res_pci_mem1.start; ++ iomem_resource.end = rc32434_res_pci_mem1.end; ++*/ ++ ++ pcicValue = rc32434_pci->pcic; ++ pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN; ++ if (!((pcicValue == PCIM_H_EA) || ++ (pcicValue == PCIM_H_IA_FIX) || ++ (pcicValue == PCIM_H_IA_RR))) { ++ /* Not in Host Mode, return ERROR */ ++ return -1; ++ } ++ ++ /* Enables the Idle Grant mode, Arbiter Parking */ ++ pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m); ++ rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */ ++ /* Zero out the PCI status & PCI Status Mask */ ++ for(;;) { ++ pcicData = rc32434_pci->pcis; ++ if (!(pcicData & PCIS_rip_m)) ++ break; ++ } ++ ++ rc32434_pci->pcis = 0; ++ rc32434_pci->pcism = 0xFFFFFFFF; ++ /* Zero out the PCI decoupled registers */ ++ rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */ ++ rc32434_pci->pcidas=0; /* clear the status */ ++ rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */ ++ /* Mask PCI Messaging Interrupts */ ++ rc32434_pci_msg->pciiic = 0; ++ rc32434_pci_msg->pciiim = 0xFFFFFFFF; ++ rc32434_pci_msg->pciioic = 0; ++ rc32434_pci_msg->pciioim = 0; ++ ++ /* Setup PCILB0 as Memory Window */ ++ rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START); ++ ++ /* setup the PCI map address as same as the local address */ ++ ++ rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START); ++ ++ /* Setup PCILBA1 as MEM */ ++#ifdef __MIPSEB__ ++ rc32434_pci->pcilba[0].c = ( ((SIZE_16MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m); ++#else ++ rc32434_pci->pcilba[0].c = ( ((SIZE_16MB & 0x1f) << PCILBAC_size_b)); ++#endif ++ dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */ ++ ++ rc32434_pci->pcilba[1].a = 0x60000000; ++ ++ rc32434_pci->pcilba[1].m = 0x60000000; ++ /* setup PCILBA2 as IO Window*/ ++#ifdef __MIPSEB__ ++ rc32434_pci->pcilba[1].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m); ++#else ++ rc32434_pci->pcilba[1].c = ((SIZE_256MB & 0x1f) << PCILBAC_size_b); ++#endif ++ dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */ ++ rc32434_pci->pcilba[2].a = 0x18C00000; ++ ++ rc32434_pci->pcilba[2].m = 0x18FFFFFF; ++ /* setup PCILBA2 as IO Window*/ ++#ifdef __MIPSEB__ ++ rc32434_pci->pcilba[2].c = ( ((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCILBAC_sb_m); ++#else ++ rc32434_pci->pcilba[2].c = ((SIZE_4MB & 0x1f) << PCILBAC_size_b); ++#endif ++ ++ dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */ ++ ++ ++ rc32434_pci->pcilba[3].a = 0x18800000; ++ ++ rc32434_pci->pcilba[3].m = 0x18800000; ++ /* Setup PCILBA3 as IO Window */ ++ ++#ifdef __MIPSEB__ ++ rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCILBAC_sb_m); ++#else ++ rc32434_pci->pcilba[3].c = (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m); ++#endif ++ dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */ ++ ++ pciConfigAddr = (unsigned int)(0x80000004); ++ for(loopCount = 0; loopCount < 24; loopCount++){ ++ rc32434_pci->pcicfga = pciConfigAddr; ++ dummyRead = rc32434_pci->pcicfga; ++ rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount]; ++ dummyRead=rc32434_pci->pcicfgd; ++ pciConfigAddr += 4; ++ } ++ rc32434_pci->pcitc=(unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b) | ++ ((PCITC_DTIMER_VAL&0xff)<<PCITC_dtimer_b); ++ ++ pciCntlVal = rc32434_pci->pcic; ++ pciCntlVal &= ~(PCIC_tnr_m); ++ rc32434_pci->pcic = pciCntlVal; ++ pciCntlVal = rc32434_pci->pcic; ++ ++ register_pci_controller(&rc32434_controller); ++ ++ rc32434_sync(); ++ return 0; ++} ++ ++arch_initcall(rc32434_pcibridge_init); ++ ++/* Do platform specific device initialization at pci_enable_device() time */ ++int pcibios_plat_dev_init(struct pci_dev *dev) ++{ ++ return 0; ++} +diff -Nur linux-2.6.15/drivers/pci/access.c linux-2.6.15-openwrt/drivers/pci/access.c +--- linux-2.6.15/drivers/pci/access.c 2006-01-03 04:21:10.000000000 +0100 ++++ linux-2.6.15-openwrt/drivers/pci/access.c 2006-01-10 00:43:10.000000000 +0100 +@@ -21,6 +21,7 @@ + #define PCI_word_BAD (pos & 1) + #define PCI_dword_BAD (pos & 3) + ++#ifdef __MIPSEB__ + #define PCI_OP_READ(size,type,len) \ + int pci_bus_read_config_##size \ + (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \ +@@ -31,11 +32,32 @@ + if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ + spin_lock_irqsave(&pci_lock, flags); \ + res = bus->ops->read(bus, devfn, pos, len, &data); \ ++ if (len == 1) \ ++ *value = (type)((data >> 24) & 0xff); \ ++ else if (len == 2) \ ++ *value = (type)((data >> 16) & 0xffff); \ ++ else \ + *value = (type)data; \ + spin_unlock_irqrestore(&pci_lock, flags); \ + return res; \ + } ++#else + ++#define PCI_OP_READ(size,type,len) \ ++int pci_bus_read_config_##size \ ++ (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \ ++{ \ ++ int res; \ ++ unsigned long flags; \ ++ u32 data = 0; \ ++ if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \ ++ spin_lock_irqsave(&pci_lock, flags); \ ++ res = bus->ops->read(bus, devfn, pos, len, &data); \ ++ *value = (type)data; \ ++ spin_unlock_irqrestore(&pci_lock, flags); \ ++ return res; \ ++} ++#endif + #define PCI_OP_WRITE(size,type,len) \ + int pci_bus_write_config_##size \ + (struct pci_bus *bus, unsigned int devfn, int pos, type value) \ |