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| author | Felix Fietkau <nbd@nbd.name> | 2016-05-14 20:24:37 +0200 |
|---|---|---|
| committer | Felix Fietkau <nbd@nbd.name> | 2016-05-15 20:55:39 +0200 |
| commit | 5b34dffcbd6175d92f871b69098e027341b6c82e (patch) | |
| tree | 4435dd82308ac86ab73aaaf8de0b83d223ab8b2b /target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch | |
| parent | e30608b736f44e70da6bd29fbcfdc9dd5ec42f02 (diff) | |
| download | master-31e0f0ae-5b34dffcbd6175d92f871b69098e027341b6c82e.tar.gz master-31e0f0ae-5b34dffcbd6175d92f871b69098e027341b6c82e.tar.bz2 master-31e0f0ae-5b34dffcbd6175d92f871b69098e027341b6c82e.zip | |
ar71xx: fix DDR write buffer flushing issues with 4.4
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch b/target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch new file mode 100644 index 0000000000..09e6617b90 --- /dev/null +++ b/target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch @@ -0,0 +1,31 @@ +From: Felix Fietkau <nbd@nbd.name> +Date: Sat, 14 May 2016 20:20:04 +0200 +Subject: [PATCH] MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer + SoCs + +AR913x, AR724x and AR933x are the only SoCs where the +ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c +Invert the logic to make the code compatible with AR95xx + +Signed-off-by: Felix Fietkau <nbd@nbd.name> +--- + +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -46,12 +46,12 @@ void ath79_ddr_ctrl_init(void) + { + ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, + AR71XX_DDR_CTRL_SIZE); +- if (soc_is_ar71xx() || soc_is_ar934x()) { +- ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c; +- ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c; +- } else { ++ if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) { + ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c; + ath79_ddr_pci_win_base = 0; ++ } else { ++ ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c; ++ ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c; + } + } + EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init); |