diff options
| author | Gabor Juhos <juhosg@openwrt.org> | 2013-03-04 11:48:15 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2013-03-04 11:48:15 +0000 |
| commit | 1d55249d7cf3811b02cd9221b5ae93df14a2ff9a (patch) | |
| tree | 1e562a1548e9d6f3b10ad54792f652091e4174f1 /target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch | |
| parent | 64a9fe2894ab05e504cfcb824701e59d484f5f53 (diff) | |
| download | master-31e0f0ae-1d55249d7cf3811b02cd9221b5ae93df14a2ff9a.tar.gz master-31e0f0ae-1d55249d7cf3811b02cd9221b5ae93df14a2ff9a.tar.bz2 master-31e0f0ae-1d55249d7cf3811b02cd9221b5ae93df14a2ff9a.zip | |
ar71xx: use backported QCA955x patches
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 35878
Diffstat (limited to 'target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch index fb7d169ad6..5cb7584fdc 100644 --- a/target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-3.8/601-MIPS-ath79-add-more-register-defines.patch @@ -42,12 +42,17 @@ #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) #define AR934X_SRIF_SIZE 0x1000 -@@ -112,6 +124,10 @@ - #define QCA955X_EHCI0_BASE 0x1b000000 - #define QCA955X_EHCI1_BASE 0x1b400000 - #define QCA955X_EHCI_SIZE 0x200 +@@ -107,11 +119,15 @@ + #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) + #define QCA955X_PCI_CTRL_SIZE 0x100 + +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40 + #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define QCA955X_WMAC_SIZE 0x20000 + #define QCA955X_EHCI0_BASE 0x1b000000 + #define QCA955X_EHCI1_BASE 0x1b400000 + #define QCA955X_EHCI_SIZE 0x1000 +#define QCA955X_NFC_BASE 0x1b800200 +#define QCA955X_NFC_SIZE 0xb8 @@ -105,7 +110,7 @@ #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -@@ -378,16 +408,83 @@ +@@ -379,16 +409,83 @@ #define AR913X_RESET_USB_HOST BIT(5) #define AR913X_RESET_USB_PHY BIT(4) @@ -189,7 +194,7 @@ #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) -@@ -529,6 +626,12 @@ +@@ -530,6 +627,12 @@ #define AR71XX_GPIO_REG_INT_ENABLE 0x24 #define AR71XX_GPIO_REG_FUNC 0x28 @@ -202,7 +207,7 @@ #define AR934X_GPIO_REG_FUNC 0x6c #define AR71XX_GPIO_COUNT 16 -@@ -560,4 +663,133 @@ +@@ -561,4 +664,133 @@ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 |