diff options
| author | Jonas Gorski <jogo@openwrt.org> | 2015-05-21 19:32:46 +0000 |
|---|---|---|
| committer | Jonas Gorski <jogo@openwrt.org> | 2015-05-21 19:32:46 +0000 |
| commit | 76d079204df113afa9e382a43abb5e1a2135150d (patch) | |
| tree | 8e472ab203e8d6a47dc2e285b3becbfca35d04c6 /target/linux/ar71xx/patches-3.18/605-MIPS-ath79-db120-fixes.patch | |
| parent | 072937888e133f5e97fd05a7496eaf7eeae04079 (diff) | |
| download | master-31e0f0ae-76d079204df113afa9e382a43abb5e1a2135150d.tar.gz master-31e0f0ae-76d079204df113afa9e382a43abb5e1a2135150d.tar.bz2 master-31e0f0ae-76d079204df113afa9e382a43abb5e1a2135150d.zip | |
kernel: update 3.18 to 3.18.14
Changelogs:
* https://www.kernel.org/pub/linux/kernel/v3.x/ChangeLog-3.18.12
* https://www.kernel.org/pub/linux/kernel/v3.x/ChangeLog-3.18.13
* https://www.kernel.org/pub/linux/kernel/v3.x/ChangeLog-3.18.14
Build tested on brcm63xx and ipq806x, runtested on brcm63xx.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45711
Diffstat (limited to 'target/linux/ar71xx/patches-3.18/605-MIPS-ath79-db120-fixes.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-3.18/605-MIPS-ath79-db120-fixes.patch | 47 |
1 files changed, 23 insertions, 24 deletions
diff --git a/target/linux/ar71xx/patches-3.18/605-MIPS-ath79-db120-fixes.patch b/target/linux/ar71xx/patches-3.18/605-MIPS-ath79-db120-fixes.patch index d62263fcdf..080165a802 100644 --- a/target/linux/ar71xx/patches-3.18/605-MIPS-ath79-db120-fixes.patch +++ b/target/linux/ar71xx/patches-3.18/605-MIPS-ath79-db120-fixes.patch @@ -67,14 +67,6 @@ }, }; -+static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = { -+ .mode = AR8327_PAD_MAC_RGMII, -+ .txclk_delay_en = true, -+ .rxclk_delay_en = true, -+ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, -+ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, -+}; -+ -static struct spi_board_info db120_spi_info[] = { - { - .bus_num = 0, @@ -82,6 +74,17 @@ - .max_speed_hz = 25000000, - .modalias = "s25sl064a", - } ++static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = { ++ .mode = AR8327_PAD_MAC_RGMII, ++ .txclk_delay_en = true, ++ .rxclk_delay_en = true, ++ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, ++ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, + }; + +-static struct ath79_spi_platform_data db120_spi_data = { +- .bus_num = 0, +- .num_chipselect = 1, +static struct ar8327_led_cfg db120_ar8327_led_cfg = { + .led_ctrl0 = 0x00000000, + .led_ctrl1 = 0xc737c737, @@ -90,21 +93,6 @@ + .open_drain = true, }; --static struct ath79_spi_platform_data db120_spi_data = { -- .bus_num = 0, -- .num_chipselect = 1, -+static struct ar8327_platform_data db120_ar8327_data = { -+ .pad0_cfg = &db120_ar8327_pad0_cfg, -+ .port0_cfg = { -+ .force_link = 1, -+ .speed = AR8327_PORT_SPEED_1000, -+ .duplex = 1, -+ .txpause = 1, -+ .rxpause = 1, -+ }, -+ .led_cfg = &db120_ar8327_led_cfg, - }; - -#ifdef CONFIG_PCI -static struct ath9k_platform_data db120_ath9k_data; - @@ -123,7 +111,18 @@ -{ - memcpy(db120_ath9k_data.eeprom_data, eeprom, - sizeof(db120_ath9k_data.eeprom_data)); -- ++static struct ar8327_platform_data db120_ar8327_data = { ++ .pad0_cfg = &db120_ar8327_pad0_cfg, ++ .port0_cfg = { ++ .force_link = 1, ++ .speed = AR8327_PORT_SPEED_1000, ++ .duplex = 1, ++ .txpause = 1, ++ .rxpause = 1, ++ }, ++ .led_cfg = &db120_ar8327_led_cfg, ++}; + - ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init); - ath79_register_pci(); -} |