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| author | Gabor Juhos <juhosg@openwrt.org> | 2011-05-31 22:53:29 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2011-05-31 22:53:29 +0000 |
| commit | e11b9c8371ce855d10846e764267d9ae68694f27 (patch) | |
| tree | 3eee276078932e644fce4b812ca2eef0343bb0a8 /target/linux/ar71xx/files/arch/mips/include | |
| parent | 0bf4478d3784f4c22e22367487c60cdff756ab54 (diff) | |
| download | master-31e0f0ae-e11b9c8371ce855d10846e764267d9ae68694f27.tar.gz master-31e0f0ae-e11b9c8371ce855d10846e764267d9ae68694f27.tar.bz2 master-31e0f0ae-e11b9c8371ce855d10846e764267d9ae68694f27.zip | |
ar71xx: add AR933x specific frequency initialization code
SVN-Revision: 27056
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips/include')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h index 47ad8a4bae..759c8e6ab3 100644 --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h @@ -188,6 +188,24 @@ extern enum ar71xx_soc_type ar71xx_soc; #define AR91XX_ETH0_PLL_SHIFT 20 #define AR91XX_ETH1_PLL_SHIFT 22 +#define AR933X_PLL_CPU_CONFIG_REG 0x00 +#define AR933X_PLL_CLOCK_CTRL_REG 0x08 + +#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 +#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 +#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 +#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 +#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 + #define AR934X_PLL_REG_CPU_CONFIG 0x00 #define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8 @@ -579,6 +597,9 @@ void ar71xx_ddr_flush(u32 reg); #define AR724X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_BOOTSTRAP 0xac +#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + #define AR934X_RESET_REG_RESET_MODULE 0x1c #define AR934X_RESET_REG_BOOTSTRAP 0xb0 /* 0 - 25MHz 1 - 40 MHz */ |