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| author | Gabor Juhos <juhosg@openwrt.org> | 2013-09-02 16:09:12 +0000 |
|---|---|---|
| committer | Gabor Juhos <juhosg@openwrt.org> | 2013-09-02 16:09:12 +0000 |
| commit | 122a61aa49a92435e6046c1a91e2214972af6e47 (patch) | |
| tree | cef5e02d841e35449fc6ee08b49597c37308555c /target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c | |
| parent | a6b26d9aead9f0142353a48f0ce154fc46d47fab (diff) | |
| download | master-31e0f0ae-122a61aa49a92435e6046c1a91e2214972af6e47.tar.gz master-31e0f0ae-122a61aa49a92435e6046c1a91e2214972af6e47.tar.bz2 master-31e0f0ae-122a61aa49a92435e6046c1a91e2214972af6e47.zip | |
ar71xx: configure OBS4 line on TL-WR841N-v8/MR3420v2
It also fixes USB Power on MR3420v2.
This time we took the information from the source of GPL:
http://www.mail-archive.com/openwrt-devel@lists.openwrt.org/msg18970.html
Confirmed and tested:
https://dev.openwrt.org/ticket/13201#comment:41
Thanks to oguretsagressive for testing.
Signed-off-by: Dmytro <dioptimizer@gmail.com>
SVN-Revision: 37878
Diffstat (limited to 'target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c')
| -rw-r--r-- | target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c index e376ae5a42..6d2654b184 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c @@ -132,8 +132,14 @@ static void __init tl_ap123_setup(void) u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); - /* Disable JTAG, enabling GPIOs 0-4 */ - ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE); + /* Disable JTAG, enabling GPIOs 0-3 */ + /* Configure OBS4 line, for GPIO 4*/ + ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE, + AR934X_GPIO_FUNC_CLK_OBS4_EN); + + /* config gpio4 as normal gpio function */ + ath79_gpio_output_select(TL_MR3420V2_GPIO_USB_POWER, + AR934X_GPIO_OUT_GPIO); ath79_register_m25p80(&tl_wr841n_v8_flash_data); |