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authorGabor Juhos <juhosg@openwrt.org>2008-08-07 13:50:02 +0000
committerGabor Juhos <juhosg@openwrt.org>2008-08-07 13:50:02 +0000
commitdb4d23b4577ebf718406129a59c87beb20594c68 (patch)
treea5ba9b630f965637a010cee2088af4d57efc7f29 /target/linux/adm5120/files-2.6.26/include/asm-mips/mach-adm5120/war.h
parent34a16898a1874c3e319a145477b15e1a244efa55 (diff)
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add 2.6.26 specific files
SVN-Revision: 12239
Diffstat (limited to 'target/linux/adm5120/files-2.6.26/include/asm-mips/mach-adm5120/war.h')
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diff --git a/target/linux/adm5120/files-2.6.26/include/asm-mips/mach-adm5120/war.h b/target/linux/adm5120/files-2.6.26/include/asm-mips/mach-adm5120/war.h
new file mode 100644
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--- /dev/null
+++ b/target/linux/adm5120/files-2.6.26/include/asm-mips/mach-adm5120/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_ADM5120_WAR_H
+#define __ASM_MIPS_MACH_ADM5120_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 0
+#define MIPS_CACHE_SYNC_WAR 0
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 0
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif /* __ASM_MIPS_MACH_ADM5120_WAR_H */