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| author | John Crispin <john@openwrt.org> | 2011-07-17 19:27:24 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2011-07-17 19:27:24 +0000 |
| commit | c0c7c82a2f9f9959c24563becba12c380294cded (patch) | |
| tree | 8c0f378e446034bf9e87c73be630b142f3998142 /package | |
| parent | a6ceecd9738671fbbf36b1a0508f449c446a8ed2 (diff) | |
| download | master-31e0f0ae-c0c7c82a2f9f9959c24563becba12c380294cded.tar.gz master-31e0f0ae-c0c7c82a2f9f9959c24563becba12c380294cded.tar.bz2 master-31e0f0ae-c0c7c82a2f9f9959c24563becba12c380294cded.zip | |
revert parts of r27488 to uboot-lantiq
Signed-off-by: Luka Perkov <openwrt@lukaperkov.net>
SVN-Revision: 27663
Diffstat (limited to 'package')
| -rw-r--r-- | package/uboot-lantiq/files/board/infineon/easy50712/danube.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/package/uboot-lantiq/files/board/infineon/easy50712/danube.c b/package/uboot-lantiq/files/board/infineon/easy50712/danube.c index 51b7577edb..e3845cb38f 100644 --- a/package/uboot-lantiq/files/board/infineon/easy50712/danube.c +++ b/package/uboot-lantiq/files/board/infineon/easy50712/danube.c @@ -259,12 +259,12 @@ static int external_switch_init(void) /* earlier no valid response is available, at least on Twinpass & Tantos @ 111MHz, M4530 platform */ udelay(100000); - printf("\nsearching for Samurai switch ... "); + debug("\nsearching for Samurai switch ... "); if ( (miiphy_read(name, PHYADDR(SAMURAI_ID_REG0), &chipid0)==0) && (miiphy_read(name, PHYADDR(SAMURAI_ID_REG1), &chipid1)==0) ) { if (((chipid0 & 0xFFF0) == ID_SAMURAI_0) && ((chipid1 & 0x000F) == ID_SAMURAI_1)) { - printf("found"); + debug("found"); /* enable "Crossover Auto Detect" + defaults */ /* P0 */ @@ -288,11 +288,10 @@ static int external_switch_init(void) } } - printf("%04X %04x\n", chipid0, chipid1); - printf("\nsearching for TANTOS switch ... "); + debug("\nsearching for TANTOS switch ... "); if (miiphy_read(name, PHYADDR(0x101), &chipid0) == 0) { if (chipid0 == ID_TANTOS) { - printf("found"); + debug("found"); /* P5 Basic Control: Force Link Up */ miiphy_write(name, PHYADDR(0xA1), 0x0004); |