diff options
| author | Felix Fietkau <nbd@openwrt.org> | 2010-06-30 00:10:44 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2010-06-30 00:10:44 +0000 |
| commit | 96436fac60ccb9bb5fb3e26589dcf7fc5d89ec89 (patch) | |
| tree | 0a912d711456178769f777b1baf75c71d354275c /package/mac80211 | |
| parent | bc13e4c08a07eca48a0e27088378f31822e72e02 (diff) | |
| download | master-31e0f0ae-96436fac60ccb9bb5fb3e26589dcf7fc5d89ec89.tar.gz master-31e0f0ae-96436fac60ccb9bb5fb3e26589dcf7fc5d89ec89.tar.bz2 master-31e0f0ae-96436fac60ccb9bb5fb3e26589dcf7fc5d89ec89.zip | |
ath9k: fix TSF across hardware resets on AR913x
SVN-Revision: 21989
Diffstat (limited to 'package/mac80211')
| -rw-r--r-- | package/mac80211/patches/510-ar9100_tsf_preserve.patch | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/package/mac80211/patches/510-ar9100_tsf_preserve.patch b/package/mac80211/patches/510-ar9100_tsf_preserve.patch new file mode 100644 index 0000000000..3af78dabbd --- /dev/null +++ b/package/mac80211/patches/510-ar9100_tsf_preserve.patch @@ -0,0 +1,39 @@ +--- a/drivers/net/wireless/ath/ath9k/hw.c ++++ b/drivers/net/wireless/ath/ath9k/hw.c +@@ -1280,7 +1280,8 @@ int ath9k_hw_reset(struct ath_hw *ah, st + macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; + + /* For chips on which RTC reset is done, save TSF before it gets cleared */ +- if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) ++ if (AR_SREV_9100(ah) || ++ (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) + tsf = ath9k_hw_gettsf64(ah); + + saveLedState = REG_READ(ah, AR_CFG_LED) & +@@ -1312,7 +1313,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st + } + + /* Restore TSF */ +- if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) ++ if (tsf) + ath9k_hw_settsf64(ah, tsf); + + if (AR_SREV_9280_10_OR_LATER(ah)) +@@ -1325,6 +1326,17 @@ int ath9k_hw_reset(struct ath_hw *ah, st + if (r) + return r; + ++ /* ++ * Some AR91xx SoC devices frequently fail to accept TSF writes ++ * right after the chip reset. When that happens, write a new ++ * value after the initvals have been applied, with an offset ++ * based on measured time differences ++ */ ++ if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { ++ tsf += 1500; ++ ath9k_hw_settsf64(ah, tsf); ++ } ++ + /* Setup MFP options for CCMP */ + if (AR_SREV_9280_20_OR_LATER(ah)) { + /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt |