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| author | Felix Fietkau <nbd@openwrt.org> | 2015-09-16 07:56:41 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-09-16 07:56:41 +0000 |
| commit | 5fa9ed8c1064bb7a4d275ce4d2458a773f491675 (patch) | |
| tree | a34e89ac12e470033c1550564016abc48f39f1c1 /package/kernel | |
| parent | f74116e59942d9773459b1de0882901b21f60bbd (diff) | |
| download | master-31e0f0ae-5fa9ed8c1064bb7a4d275ce4d2458a773f491675.tar.gz master-31e0f0ae-5fa9ed8c1064bb7a4d275ce4d2458a773f491675.tar.bz2 master-31e0f0ae-5fa9ed8c1064bb7a4d275ce4d2458a773f491675.zip | |
ath9k: enable hw manual peak calibration for QCA9561
This patch fix https://lists.openwrt.org/pipermail/openwrt-devel/
2015-August/034979.html. As the peak detect calibration is set
incorrectly.
Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 46948
Diffstat (limited to 'package/kernel')
| -rw-r--r-- | package/kernel/mac80211/patches/333-ath9k-enable-hw-manual-peak-calibration-for-QCA9561.patch | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/package/kernel/mac80211/patches/333-ath9k-enable-hw-manual-peak-calibration-for-QCA9561.patch b/package/kernel/mac80211/patches/333-ath9k-enable-hw-manual-peak-calibration-for-QCA9561.patch new file mode 100644 index 0000000000..faf6cdc163 --- /dev/null +++ b/package/kernel/mac80211/patches/333-ath9k-enable-hw-manual-peak-calibration-for-QCA9561.patch @@ -0,0 +1,33 @@ +From: Miaoqing Pan <miaoqing@qca.qualcomm.com> +Date: Tue, 1 Sep 2015 10:56:09 +0800 +Subject: [PATCH] ath9k: enable hw manual peak calibration for QCA9561 + +This patch fix https://lists.openwrt.org/pipermail/openwrt-devel/ +2015-August/034979.html. As the peak detect calibration is set +incorrectly. + +Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com> +--- + +--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c ++++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c +@@ -1249,7 +1249,8 @@ static void ar9003_hw_manual_peak_cal(st + REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), + AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR, 0x0); + +- if (AR_SREV_9003_PCOEM(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) { ++ if (AR_SREV_9003_PCOEM(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || ++ AR_SREV_9561(ah)) { + if (is_2g) + REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), + AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR, +@@ -1640,7 +1641,8 @@ static bool ar9003_hw_init_cal_soc(struc + + skip_tx_iqcal: + if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) { +- if (AR_SREV_9330_11(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah)) { ++ if (AR_SREV_9330_11(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah) || ++ AR_SREV_9561(ah)) { + for (i = 0; i < AR9300_MAX_CHAINS; i++) { + if (!(ah->rxchainmask & (1 << i))) + continue; |