ralink: add mt7621 support

there are still various missing pieces for full support.

Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 39040

20 files changed, 7513 insertions, 1 deletions

diff --git a/target/linux/ramips/Makefile b/target/linux/ramips/Makefile
index 84ce8f0280..ad3f690a88 100644
--- a/target/linux/ramips/Makefile
+++ b/target/linux/ramips/Makefile
@@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
 ARCH:=mipsel
 BOARD:=ramips
 BOARDNAME:=Ralink RT288x/RT3xxx
-SUBTARGETS:=rt305x mt7620a mt7620n rt3883 rt288x
+SUBTARGETS:=rt305x mt7620a mt7620n mt7621 rt3883 rt288x
 FEATURES:=squashfs gpio
 
 LINUX_VERSION:=3.10.21
diff --git a/target/linux/ramips/dts/MT7621.dts b/target/linux/ramips/dts/MT7621.dts
new file mode 100644
index 0000000000..834f59c401
--- /dev/null
+++ b/target/linux/ramips/dts/MT7621.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+
+/include/ "mt7621.dtsi"
+
+/ {
+	compatible = "ralink,mt7621-eval-board", "ralink,mt7621-soc";
+	model = "Ralink MT7621 evaluation board";
+
+	memory@0 {
+		reg = <0x0 0x2000000>;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,57600";
+	};
+};
diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi
new file mode 100644
index 0000000000..9fa9d0a5fa
--- /dev/null
+++ b/target/linux/ramips/dts/mt7621.dtsi
@@ -0,0 +1,245 @@
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "ralink,mtk7620a-soc";
+
+	cpus {
+		cpu@0 {
+			compatible = "mips,mips24KEc";
+		};
+	};
+
+	cpuintc: cpuintc@0 {
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		compatible = "mti,cpu-interrupt-controller";
+	};
+
+	palmbus@1E000000 {
+		compatible = "palmbus";
+		reg = <0x1E000000 0x100000>;
+                ranges = <0x0 0x1E000000 0x0FFFFF>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		sysc@0 {
+			compatible = "mtk,mt7621-sysc";
+			reg = <0x0 0x100>;
+		};
+
+		wdt@100 {
+			compatible = "mtk,mt7621-wdt";
+			reg = <0x100 0x100>;
+		};
+
+		gpio@600 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			compatible = "mtk,mt7621-gpio";
+			reg = <0x600 0x100>;
+
+			gpio0: bank@0 {
+				reg = <0>;
+				compatible = "mtk,mt7621-gpio-bank";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpio1: bank@1 {
+				reg = <1>;
+				compatible = "mtk,mt7621-gpio-bank";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpio2: bank@2 {
+				reg = <2>;
+				compatible = "mtk,mt7621-gpio-bank";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+
+		memc@5000 {
+			compatible = "mtk,mt7621-memc";
+			reg = <0x300 0x100>;
+		};
+
+		uartlite@c00 {
+			compatible = "ns16550a";
+			reg = <0xc00 0x100>;
+
+/*			interrupt-parent = <&gic>;
+			interrupts = <26>;*/
+
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			no-loopback-test;
+		};
+
+		spi@b00 {
+			status = "okay";
+
+			compatible = "ralink,mt7621-spi";
+			reg = <0xb00 0x100>;
+
+			resets = <&rstctrl 18>;
+			reset-names = "spi";
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+/*			pinctrl-names = "default";
+			pinctrl-0 = <&spi_pins>;*/
+
+			m25p80@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "en25q64";
+				reg = <0 0>;
+				linux,modalias = "m25p80", "en25q64";
+				spi-max-frequency = <10000000>;
+
+				m25p,chunked-io;
+
+				partition@0 {
+					label = "u-boot";
+					reg = <0x0 0x30000>;
+					read-only;
+				};
+
+				partition@30000 {
+					label = "u-boot-env";
+					reg = <0x30000 0x10000>;
+					read-only;
+				};
+
+				factory: partition@40000 {
+					label = "factory";
+					reg = <0x40000 0x10000>;
+					read-only;
+				};
+
+				partition@50000 {
+					label = "firmware";
+					reg = <0x50000 0x7a0000>;
+				};
+
+				partition@7f0000 {
+					label = "test";
+					reg = <0x7f0000 0x10000>;
+				};
+			};
+		};
+	};
+
+	rstctrl: rstctrl {
+		compatible = "ralink,rt2880-reset";
+		#reset-cells = <1>;
+	};
+
+	sdhci@1E130000 {
+		compatible = "ralink,mt7620a-sdhci";
+		reg = <0x1E130000 4000>;
+
+		interrupt-parent = <&gic>;
+		interrupts = <20>;
+	};
+
+	xhci@1E1C0000 {
+		compatible = "xhci-platform1";
+		reg = <0x1E1C0000 4000>;
+
+		interrupt-parent = <&gic>;
+		interrupts = <22>;
+	};
+
+	gic: gic@1fbc0000 {
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		compatible = "ralink,mt7621-gic";
+		reg = < 0x1fbc0000 0x80 /* gic */
+			0x1fbf0000 0x8000 /* cpc */
+			0x1fbf8000 0x8000 /* gpmc */
+		>;
+	};
+
+	nand@1e003000 {
+		compatible = "mtk,mt7621-nand";
+		bank-width = <2>;
+		reg = <0x1e003000 0x800
+			0x1e003800 0x800>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "uboot";
+			reg = <0x00000 0x80000>; /* 64 KB */
+		};
+		partition@80000 {
+			label = "uboot_env";
+			reg = <0x80000 0x80000>; /* 64 KB */
+		};
+		partition@100000 {
+			label = "factory";
+			reg = <0x100000 0x40000>;
+		};
+		partition@140000 {
+			label = "rootfs";
+			reg = <0x140000 0xec0000>;
+		};
+	};
+
+	ethernet@1e100000 {
+		compatible = "ralink,mt7621-eth";
+		reg = <0x1e100000 10000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ralink,port-map = "llllw";
+		
+		interrupt-parent = <&gic>;
+		interrupts = <3>;
+
+/*		resets = <&rstctrl 21 &rstctrl 23>;
+		reset-names = "fe", "esw";
+
+		port@4 {
+			compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
+			reg = <4>;
+
+			status = "disabled";
+		};
+
+		port@5 {
+			compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
+			reg = <5>;
+
+			status = "disabled";
+		};
+*/
+		mdio-bus {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			phy1f: ethernet-phy@1f {
+				reg = <0x1f>;
+				phy-mode = "rgmii";
+		
+				interrupt-parent = <&gic>;
+				interrupts = <23>;
+			};
+		};
+	};
+
+	gsw@1e110000 {
+		compatible = "ralink,mt7620a-gsw";
+		reg = <0x1e110000 8000>;
+
+	};
+};
diff --git a/target/linux/ramips/image/Makefile b/target/linux/ramips/image/Makefile
index 32047ccfed..82addb27f8 100644
--- a/target/linux/ramips/image/Makefile
+++ b/target/linux/ramips/image/Makefile
@@ -29,10 +29,16 @@ define kernel_entry
 -a 0x88000000 -e 0x88000000
 endef
 else
+ifeq ($(CONFIG_SOC_MT7621),y)
+define kernel_entry
+-a 0x80001000 -e 0x80001000
+endef
+else
 define kernel_entry
 -a 0x80000000 -e 0x80000000
 endef
 endif
+endif
 
 define MkCombineduImage
 	$(call PatchKernelLzma,$(2),$(3))
@@ -649,6 +655,19 @@ endif
 
 
 #
+# MT7621 Profiles
+#
+
+Image/Build/Profile/MT7621=$(call BuildFirmware/Default4M/$(1),$(1),mt7621,MT7621)
+
+ifeq ($(SUBTARGET),mt7621)
+define Image/Build/Profile/Default
+	$(call Image/Build/Profile/MT7621,$(1))
+endef
+endif
+
+
+#
 # Generic Targets
 #
 define Image/BuildKernel
diff --git a/target/linux/ramips/mt7620a/config-3.10 b/target/linux/ramips/mt7620a/config-3.10
index 21d5be1d52..1320574b97 100644
--- a/target/linux/ramips/mt7620a/config-3.10
+++ b/target/linux/ramips/mt7620a/config-3.10
@@ -147,6 +147,7 @@ CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 CONFIG_SOC_MT7620=y
+# CONFIG_SOC_MT7621 is not set
 # CONFIG_SOC_RT288X is not set
 # CONFIG_SOC_RT305X is not set
 # CONFIG_SOC_RT3883 is not set
diff --git a/target/linux/ramips/mt7620n/config-3.10 b/target/linux/ramips/mt7620n/config-3.10
index 641c039c27..44d991b9de 100644
--- a/target/linux/ramips/mt7620n/config-3.10
+++ b/target/linux/ramips/mt7620n/config-3.10
@@ -144,6 +144,7 @@ CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 CONFIG_SOC_MT7620=y
+# CONFIG_SOC_MT7621 is not set
 # CONFIG_SOC_RT288X is not set
 # CONFIG_SOC_RT305X is not set
 # CONFIG_SOC_RT3883 is not set
diff --git a/target/linux/ramips/mt7621/config-3.10 b/target/linux/ramips/mt7621/config-3.10
new file mode 100644
index 0000000000..a94e976fc8
--- /dev/null
+++ b/target/linux/ramips/mt7621/config-3.10
@@ -0,0 +1,200 @@
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_ARCH_DISCARD_MEMBLOCK=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_BOARD_SCACHE=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+# CONFIG_CEVT_GIC is not set
+CONFIG_CEVT_R4K=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+# CONFIG_CPU_MIPS32_R1 is not set
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_MIPSR2_IRQ_EI=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_R4K_FPU=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_MT7621_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+# CONFIG_GPIO_MT7621 is not set
+CONFIG_GPIO_RALINK=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_KVM=y
+CONFIG_HAVE_MACH_CLKDEV=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HW_HAS_PCI=y
+CONFIG_HW_RANDOM=m
+CONFIG_HZ_PERIODIC=y
+CONFIG_IMAGE_CMDLINE_HACK=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_CPU=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_GIC=y
+CONFIG_IRQ_WORK=y
+CONFIG_M25PXX_USE_FAST_READ=y
+CONFIG_MDIO_BOARDINFO=y
+# CONFIG_MII is not set
+CONFIG_MIPS=y
+CONFIG_MIPS_CMP=y
+CONFIG_MIPS_CPU_SCACHE=y
+# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
+CONFIG_MIPS_L1_CACHE_SHIFT=6
+# CONFIG_MIPS_MACHINE is not set
+CONFIG_MIPS_MT=y
+# CONFIG_MIPS_MT_DISABLED is not set
+CONFIG_MIPS_MT_FPAFF=y
+CONFIG_MIPS_MT_SMP=y
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+# CONFIG_MIPS_VPE_LOADER is not set
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MT7621_WDT is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_UIMAGE_SPLIT=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+# CONFIG_NET_RALINK is not set
+CONFIG_NLS=m
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NR_CPUS=4
+CONFIG_NR_CPUS_DEFAULT_2=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PHYLIB=y
+# CONFIG_PINCONF is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RT2880=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PINMUX=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_RALINK=y
+CONFIG_RALINK_USBPHY=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+# CONFIG_SAMSUNG_USB2PHY is not set
+# CONFIG_SAMSUNG_USB3PHY is not set
+# CONFIG_SAMSUNG_USBPHY is not set
+CONFIG_SCHED_SMT=y
+# CONFIG_SCSI_DMA is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+# CONFIG_SOC_MT7620 is not set
+CONFIG_SOC_MT7621=y
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_RT2880=y
+CONFIG_STOP_MACHINE=y
+CONFIG_SWCONFIG=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS_CMP=y
+CONFIG_SYS_SUPPORTS_MULTITHREADING=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TREE_RCU=y
+CONFIG_UIDGID_CONVERTED=y
+CONFIG_USB=m
+CONFIG_USB_ARCH_HAS_XHCI=y
+CONFIG_USB_COMMON=m
+# CONFIG_USB_EHCI_HCD is not set
+CONFIG_USB_PHY=y
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_XPS=y
+CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/ramips/mt7621/profiles/00-default.mk b/target/linux/ramips/mt7621/profiles/00-default.mk
new file mode 100644
index 0000000000..a905d1ed80
--- /dev/null
+++ b/target/linux/ramips/mt7621/profiles/00-default.mk
@@ -0,0 +1,18 @@
+#
+# Copyright (C) 2011 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+define Profile/Default
+	NAME:=Default Profile
+	PACKAGES:=\
+		kmod-usb-core kmod-usb-dwc2 \
+		kmod-ledtrig-usbdev
+endef
+
+define Profile/Default/Description
+	Default package set compatible with most boards.
+endef
+$(eval $(call Profile,Default))
diff --git a/target/linux/ramips/mt7621/target.mk b/target/linux/ramips/mt7621/target.mk
new file mode 100644
index 0000000000..98d3c6f2f5
--- /dev/null
+++ b/target/linux/ramips/mt7621/target.mk
@@ -0,0 +1,15 @@
+#
+# Copyright (C) 2009 OpenWrt.org
+#
+
+SUBTARGET:=mt7621
+BOARDNAME:=MT7621 based boards
+ARCH_PACKAGES:=ramips_24kec
+FEATURES+=usb
+CPU_TYPE:=24kec
+CPU_SUBTYPE:=dsp
+
+define Target/Description
+	Build firmware images for Ralink MT7621 based boards.
+endef
+
diff --git a/target/linux/ramips/patches-3.10/0206-MTD-add-chunked-read-io-to-m25p80.patch b/target/linux/ramips/patches-3.10/0206-MTD-add-chunked-read-io-to-m25p80.patch
new file mode 100644
index 0000000000..6018534135
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0206-MTD-add-chunked-read-io-to-m25p80.patch
@@ -0,0 +1,162 @@
+From 926ae0ca5017a421709ab0478582683c29988b05 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 27 Nov 2013 20:58:16 +0100
+Subject: [PATCH 10/20] MTD: add chunked read io to m25p80
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/devices/m25p80.c |  127 ++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 127 insertions(+)
+
+Index: linux-3.10.21/drivers/mtd/devices/m25p80.c
+===================================================================
+--- linux-3.10.21.orig/drivers/mtd/devices/m25p80.c	2013-12-09 19:34:40.828651303 +0100
++++ linux-3.10.21/drivers/mtd/devices/m25p80.c	2013-12-09 19:40:37.636659793 +0100
+@@ -392,6 +392,57 @@
+ 	return 0;
+ }
+ 
++static int m25p80_read_chunked(struct mtd_info *mtd, loff_t from, size_t len,
++	size_t *retlen, u_char *buf)
++{
++	struct m25p *flash = mtd_to_m25p(mtd);
++	struct spi_transfer t[2];
++	struct spi_message m;
++	uint8_t opcode;
++	int idx = 0;
++
++	pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
++			__func__, (u32)from, len);
++
++	spi_message_init(&m);
++	memset(t, 0, (sizeof t));
++
++	t[0].tx_buf = flash->command;
++	t[0].len = m25p_cmdsz(flash);
++	spi_message_add_tail(&t[0], &m);
++	spi_message_add_tail(&t[1], &m);
++
++	while (idx < len) {
++		int rlen = (len - idx > 4) ? (4) : (len - idx);
++
++		t[1].rx_buf = &buf[idx];
++		t[1].len = rlen;
++
++		mutex_lock(&flash->lock);
++
++		/* Wait till previous write/erase is done. */
++		if (wait_till_ready(flash)) {
++			/* REVISIT status return?? */
++			mutex_unlock(&flash->lock);
++			return 1;
++		}
++
++		/* Set up the write data buffer. */
++		opcode = OPCODE_NORM_READ;
++		flash->command[0] = opcode;
++		m25p_addr2cmd(flash, from + idx, flash->command);
++
++		spi_sync(flash->spi, &m);
++
++		*retlen = m.actual_length - m25p_cmdsz(flash) -
++			(flash->fast_read ? 1 : 0);
++
++		mutex_unlock(&flash->lock);
++		idx += rlen;
++	}
++	return 0;
++}
++
+ /*
+  * Write an address range to the flash chip.  Data must be written in
+  * FLASH_PAGESIZE chunks.  The address range may be any size provided
+@@ -479,6 +530,76 @@
+ 	return 0;
+ }
+ 
++static int m25p80_write_chunked(struct mtd_info *mtd, loff_t to, size_t len,
++	size_t *retlen, const u_char *buf)
++{
++	struct m25p *flash = mtd_to_m25p(mtd);
++	struct spi_transfer t;
++	struct spi_message m;
++	u32 i, page_size;
++	u8 tmp[8];
++
++	pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
++			__func__, (u32)to, len);
++
++	spi_message_init(&m);
++	memset(&t, 0, (sizeof t));
++
++	t.tx_buf = tmp;
++	t.len = 8;
++	spi_message_add_tail(&t, &m);
++
++	mutex_lock(&flash->lock);
++
++	/* Wait until finished previous write command. */
++	if (wait_till_ready(flash)) {
++		mutex_unlock(&flash->lock);
++		return 1;
++	}
++
++	write_enable(flash);
++
++	/* Set up the opcode in the write buffer. */
++	flash->command[0] = OPCODE_PP;
++	m25p_addr2cmd(flash, to, flash->command);
++
++	t.len = 4 + (to & 0x3);
++	if (t.len == 4)
++		t.len = 8;
++	memcpy(tmp, flash->command, 4);
++	memcpy(&tmp[4], buf, t.len - 4);
++	spi_sync(flash->spi, &m);
++	page_size = t.len - 4;
++
++	*retlen = m.actual_length - m25p_cmdsz(flash);
++
++	/* write everything in flash->page_size chunks */
++	for (i = page_size; i < len; i += page_size) {
++		page_size = len - i;
++		if (page_size > 4)
++			page_size = 4;
++
++		/* write the next page to flash */
++		m25p_addr2cmd(flash, to + i, flash->command);
++
++		memcpy(tmp, flash->command, 4);
++		memcpy(&tmp[4], buf + i, page_size);
++		t.len = 4 + page_size;
++
++		wait_till_ready(flash);
++
++		write_enable(flash);
++
++		spi_sync(flash->spi, &m);
++
++		*retlen += m.actual_length - m25p_cmdsz(flash);
++	}
++
++	mutex_unlock(&flash->lock);
++
++	return 0;
++}
++
+ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
+ 		size_t *retlen, const u_char *buf)
+ {
+@@ -1057,6 +1178,12 @@
+ 		flash->fast_read = true;
+ #endif
+ 
++	if (np && of_property_read_bool(np, "m25p,chunked-io")) {
++		dev_warn(&spi->dev, "using chunked io\n");
++		flash->mtd._read = m25p80_read_chunked;
++		flash->mtd._write = m25p80_write_chunked;
++	}
++
+ #ifdef CONFIG_M25PXX_USE_FAST_READ
+ 	flash->fast_read = true;
+ #endif
diff --git a/target/linux/ramips/patches-3.10/0500-spi-mt7621.patch b/target/linux/ramips/patches-3.10/0500-spi-mt7621.patch
new file mode 100644
index 0000000000..c14398d418
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0500-spi-mt7621.patch
@@ -0,0 +1,336 @@
+Index: linux-3.10.21/drivers/spi/spi-rt2880.c
+===================================================================
+--- linux-3.10.21.orig/drivers/spi/spi-rt2880.c	2013-12-09 20:17:54.380713104 +0100
++++ linux-3.10.21/drivers/spi/spi-rt2880.c	2013-12-09 20:35:08.004737585 +0100
+@@ -21,8 +21,11 @@
+ #include <linux/io.h>
+ #include <linux/reset.h>
+ #include <linux/spi/spi.h>
++#include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ 
++#include <ralink_regs.h>
++
+ #define DRIVER_NAME			"spi-rt2880"
+ /* only one slave is supported*/
+ #define RALINK_NUM_CHIPSELECTS		1
+@@ -63,6 +66,25 @@
+ /* SPIFIFOSTAT register bit field */
+ #define SPIFIFOSTAT_TXFULL		BIT(17)
+ 
++#define MT7621_SPI_TRANS	0x00
++#define SPITRANS_BUSY		BIT(16)
++#define MT7621_SPI_OPCODE	0x04
++#define MT7621_SPI_DATA0	0x08
++#define SPI_CTL_TX_RX_CNT_MASK	0xff
++#define SPI_CTL_START		BIT(8)
++#define MT7621_SPI_POLAR	0x38
++#define MT7621_SPI_MASTER	0x28
++#define MT7621_SPI_SPACE	0x3c
++
++struct rt2880_spi;
++
++struct rt2880_spi_ops {
++	void (*init_hw)(struct rt2880_spi *rs);
++	void (*set_cs)(struct rt2880_spi *rs, int enable);
++	int (*baudrate_set)(struct spi_device *spi, unsigned int speed);
++	unsigned int (*write_read)(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer);
++};
++
+ struct rt2880_spi {
+ 	struct spi_master	*master;
+ 	void __iomem		*base;
+@@ -70,6 +92,8 @@
+ 	unsigned int		speed;
+ 	struct clk		*clk;
+ 	spinlock_t		lock;
++
++	struct rt2880_spi_ops	*ops;
+ };
+ 
+ static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
+@@ -149,6 +173,17 @@
+ 	return 0;
+ }
+ 
++static int mt7621_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
++{
++/*	u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
++
++	// set default clock to hclk/5
++	master &= ~(0xfff << 16);
++	master |= 0x3 << 16;
++*/
++	return 0;
++}
++
+ /*
+  * called only when no transfer is active on the bus
+  */
+@@ -164,7 +199,7 @@
+ 
+ 	if (rs->speed != speed) {
+ 		dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
+-		rc = rt2880_spi_baudrate_set(spi, speed);
++		rc = rs->ops->baudrate_set(spi, speed);
+ 		if (rc)
+ 			return rc;
+ 	}
+@@ -180,6 +215,17 @@
+ 		rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
+ }
+ 
++static void mt7621_spi_set_cs(struct rt2880_spi *rs, int enable)
++{
++	u32 polar = rt2880_spi_read(rs, MT7621_SPI_POLAR);
++
++	if (enable)
++		polar |= 1;
++	else
++		polar &= ~1;
++	rt2880_spi_write(rs, MT7621_SPI_POLAR, polar);
++}
++
+ static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
+ {
+ 	int i;
+@@ -198,8 +244,26 @@
+ 	return -ETIMEDOUT;
+ }
+ 
++static inline int mt7621_spi_wait_till_ready(struct rt2880_spi *rs)
++{
++	int i;
++
++	for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
++		u32 status;
++
++		status = rt2880_spi_read(rs, MT7621_SPI_TRANS);
++		if ((status & SPITRANS_BUSY) == 0) {
++			return 0;
++		}
++		cpu_relax();
++		udelay(1);
++	}
++
++	return -ETIMEDOUT;
++}
++
+ static unsigned int
+-rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
++rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
+ {
+ 	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
+ 	unsigned count = 0;
+@@ -239,6 +303,100 @@
+ 	return count;
+ }
+ 
++static unsigned int
++mt7621_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
++{
++	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
++	struct spi_transfer *next = NULL;
++	const u8 *tx = xfer->tx_buf;
++	u8 *rx = NULL;
++	u32 trans;
++	int len = xfer->len;
++
++	if (!tx)
++		return 0;
++
++	if (!list_is_last(&xfer->transfer_list, list)) {
++		next = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list);
++		rx = next->rx_buf;
++	}
++
++	trans = rt2880_spi_read(rs, MT7621_SPI_TRANS);
++	trans &= ~SPI_CTL_TX_RX_CNT_MASK;
++
++	if (tx) {
++		u32 data0 = 0, opcode = 0;
++
++		switch (xfer->len) {
++		case 8:
++			data0 |= tx[7] << 24;
++		case 7:
++			data0 |= tx[6] << 16;
++		case 6:
++			data0 |= tx[5] << 8;
++		case 5:
++			data0 |= tx[4];
++		case 4:
++			opcode |= tx[3] << 8;
++		case 3:
++			opcode |= tx[2] << 16;
++		case 2:
++			opcode |= tx[1] << 24;
++		case 1:
++			opcode |= tx[0];
++			break;
++
++		default:
++			dev_err(&spi->dev, "trying to write too many bytes: %d\n", next->len);
++			return -EINVAL;
++		}
++
++		rt2880_spi_write(rs, MT7621_SPI_DATA0, data0);
++		rt2880_spi_write(rs, MT7621_SPI_OPCODE, opcode);
++		trans |= xfer->len;
++	}
++
++	if (rx)
++		trans |= (next->len << 4);
++	rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
++	trans |= SPI_CTL_START;
++	rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
++
++	mt7621_spi_wait_till_ready(rs);
++
++	if (rx) {
++		u32 data0 = rt2880_spi_read(rs, MT7621_SPI_DATA0);
++		u32 opcode = rt2880_spi_read(rs, MT7621_SPI_OPCODE);
++
++		switch (next->len) {
++		case 8:
++			rx[7] = (opcode >> 24) & 0xff;
++		case 7:
++			rx[6] = (opcode >> 16) & 0xff;
++		case 6:
++			rx[5] = (opcode >> 8) & 0xff;
++		case 5:
++			rx[4] = opcode & 0xff;
++		case 4:
++			rx[3] = (data0 >> 24) & 0xff;
++		case 3:
++			rx[2] = (data0 >> 16) & 0xff;
++		case 2:
++			rx[1] = (data0 >> 8) & 0xff;
++		case 1:
++			rx[0] = data0 & 0xff;
++			break;
++
++		default:
++			dev_err(&spi->dev, "trying to read too many bytes: %d\n", next->len);
++			return -EINVAL;
++		}
++		len += next->len;
++	}
++
++	return len;
++}
++
+ static int rt2880_spi_transfer_one_message(struct spi_master *master,
+ 					   struct spi_message *m)
+ {
+@@ -280,25 +438,25 @@
+ 		}
+ 
+ 		if (!cs_active) {
+-			rt2880_spi_set_cs(rs, 1);
++			rs->ops->set_cs(rs, 1);
+ 			cs_active = 1;
+ 		}
+ 
+ 		if (t->len)
+-			m->actual_length += rt2880_spi_write_read(spi, t);
++			m->actual_length += rs->ops->write_read(spi, &m->transfers, t);
+ 
+ 		if (t->delay_usecs)
+ 			udelay(t->delay_usecs);
+ 
+ 		if (t->cs_change) {
+-			rt2880_spi_set_cs(rs, 0);
++			rs->ops->set_cs(rs, 0);
+ 			cs_active = 0;
+ 		}
+ 	}
+ 
+ msg_done:
+ 	if (cs_active)
+-		rt2880_spi_set_cs(rs, 0);
++		rs->ops->set_cs(rs, 0);
+ 
+ 	m->status = status;
+ 	spi_finalize_current_message(master);
+@@ -334,8 +492,41 @@
+ 	rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
+ }
+ 
++static void mt7621_spi_reset(struct rt2880_spi *rs)
++{
++	u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
++
++	master &= ~(0xfff << 16);
++	master |= 3 << 16;
++
++	master |= 7 << 29;
++	rt2880_spi_write(rs, MT7621_SPI_MASTER, master);
++}
++
++static struct rt2880_spi_ops spi_ops[] = {
++	{
++		.init_hw = rt2880_spi_reset,
++		.set_cs = rt2880_spi_set_cs,
++		.baudrate_set = rt2880_spi_baudrate_set,
++		.write_read = rt2880_spi_write_read,
++	}, {
++		.init_hw = mt7621_spi_reset,
++		.set_cs = mt7621_spi_set_cs,
++		.baudrate_set = mt7621_spi_baudrate_set,
++		.write_read = mt7621_spi_write_read,
++	},
++};
++
++static const struct of_device_id rt2880_spi_match[] = {
++	{ .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
++	{ .compatible = "ralink,mt7621-spi", .data = &spi_ops[1] },
++	{},
++};
++MODULE_DEVICE_TABLE(of, rt2880_spi_match);
++
+ static int rt2880_spi_probe(struct platform_device *pdev)
+ {
++        const struct of_device_id *match;
+ 	struct spi_master *master;
+ 	struct rt2880_spi *rs;
+ 	unsigned long flags;
+@@ -344,6 +535,10 @@
+ 	int status = 0;
+ 	struct clk *clk;
+ 
++        match = of_match_device(rt2880_spi_match, &pdev->dev);
++	if (!match)
++		return -EINVAL;
++
+ 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	base = devm_ioremap_resource(&pdev->dev, r);
+ 	if (IS_ERR(base))
+@@ -382,12 +577,13 @@
+ 	rs->clk = clk;
+ 	rs->master = master;
+ 	rs->sys_freq = clk_get_rate(rs->clk);
++	rs->ops = (struct rt2880_spi_ops *) match->data;
+ 	dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
+ 	spin_lock_irqsave(&rs->lock, flags);
+ 
+ 	device_reset(&pdev->dev);
+ 
+-	rt2880_spi_reset(rs);
++	rs->ops->init_hw(rs);
+ 
+ 	return spi_register_master(master);
+ }
+@@ -408,12 +604,6 @@
+ 
+ MODULE_ALIAS("platform:" DRIVER_NAME);
+ 
+-static const struct of_device_id rt2880_spi_match[] = {
+-	{ .compatible = "ralink,rt2880-spi" },
+-	{},
+-};
+-MODULE_DEVICE_TABLE(of, rt2880_spi_match);
+-
+ static struct platform_driver rt2880_spi_driver = {
+ 	.driver = {
+ 		.name = DRIVER_NAME,
diff --git a/target/linux/ramips/patches-3.10/0501-MIPS-increase-GIC_INTR_MAX.patch b/target/linux/ramips/patches-3.10/0501-MIPS-increase-GIC_INTR_MAX.patch
new file mode 100644
index 0000000000..beda3d6294
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0501-MIPS-increase-GIC_INTR_MAX.patch
@@ -0,0 +1,26 @@
+From e5327a1c6969316370af5cae7cfe6b8163178575 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 2 Dec 2013 16:07:23 +0100
+Subject: [PATCH 500/507] MIPS: increase GIC_INTR_MAX
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/gic.h |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
+index b2e3e93..2902d93 100644
+--- a/arch/mips/include/asm/gic.h
++++ b/arch/mips/include/asm/gic.h
+@@ -19,7 +19,7 @@
+ #define GIC_TRIG_EDGE			1
+ #define GIC_TRIG_LEVEL			0
+ 
+-#define GIC_NUM_INTRS			(24 + NR_CPUS * 2)
++#define GIC_NUM_INTRS			(56 + NR_CPUS * 2)
+ 
+ #define MSK(n) ((1 << (n)) - 1)
+ #define REG32(addr)		(*(volatile unsigned int *) (addr))
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0502-MIPS-ralink-add-MT7621-support.patch b/target/linux/ramips/patches-3.10/0502-MIPS-ralink-add-MT7621-support.patch
new file mode 100644
index 0000000000..c2df429a62
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0502-MIPS-ralink-add-MT7621-support.patch
@@ -0,0 +1,683 @@
+From 99342a0481d49b6e1ade90fdb02f597cb75f103f Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 2 Dec 2013 16:11:09 +0100
+Subject: [PATCH 502/507] MIPS: ralink: add MT7621 support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ralink/mt7621.h |   39 +++++
+ arch/mips/ralink/Kconfig                   |   18 ++
+ arch/mips/ralink/Makefile                  |    7 +-
+ arch/mips/ralink/Platform                  |    5 +
+ arch/mips/ralink/irq-gic.c                 |  255 ++++++++++++++++++++++++++++
+ arch/mips/ralink/malta-amon.c              |   81 +++++++++
+ arch/mips/ralink/mt7621.c                  |  186 ++++++++++++++++++++
+ 7 files changed, 590 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
+ create mode 100644 arch/mips/ralink/irq-gic.c
+ create mode 100644 arch/mips/ralink/malta-amon.c
+ create mode 100644 arch/mips/ralink/mt7621.c
+
+Index: linux-3.10.21/arch/mips/include/asm/mach-ralink/mt7621.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-3.10.21/arch/mips/include/asm/mach-ralink/mt7621.h	2013-12-09 19:52:51.752677298 +0100
+@@ -0,0 +1,39 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Parts of this file are based on Ralink's 2.6.21 BSP
++ *
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#ifndef _MT7621_REGS_H_
++#define _MT7621_REGS_H_
++
++#define MT7621_SYSC_BASE		0x1E000000
++
++#define SYSC_REG_CHIP_NAME0		0x00
++#define SYSC_REG_CHIP_NAME1		0x04
++#define SYSC_REG_CHIP_REV		0x0c
++#define SYSC_REG_SYSTEM_CONFIG0		0x10
++#define SYSC_REG_SYSTEM_CONFIG1		0x14
++
++#define CHIP_REV_PKG_MASK		0x1
++#define CHIP_REV_PKG_SHIFT		16
++#define CHIP_REV_VER_MASK		0xf
++#define CHIP_REV_VER_SHIFT		8
++#define CHIP_REV_ECO_MASK		0xf
++
++#define MT7621_DRAM_BASE                0x0
++#define MT7621_DDR2_SIZE_MIN		32
++#define MT7621_DDR2_SIZE_MAX		256
++
++#define MT7621_CHIP_NAME0		0x3637544D
++#define MT7621_CHIP_NAME1		0x20203132
++
++#define MIPS_GIC_IRQ_BASE           (MIPS_CPU_IRQ_BASE + 8)
++
++#endif
+Index: linux-3.10.21/arch/mips/ralink/Kconfig
+===================================================================
+--- linux-3.10.21.orig/arch/mips/ralink/Kconfig	2013-12-09 19:51:55.600675960 +0100
++++ linux-3.10.21/arch/mips/ralink/Kconfig	2013-12-09 19:52:51.756677296 +0100
+@@ -1,5 +1,10 @@
+ if RALINK
+ 
++config IRQ_INTC
++	bool
++	default y
++	depends on !SOC_MT7621
++
+ config CLKEVT_RT3352
+ 	bool "Systick Clockevent source"
+ 	depends on SOC_RT305X || SOC_MT7620
+@@ -35,6 +40,15 @@
+ 		select USB_ARCH_HAS_EHCI
+ 		select HW_HAS_PCI
+ 
++	config SOC_MT7621
++		bool "MT7621"
++		select MIPS_CPU_SCACHE
++		select SYS_SUPPORTS_MULTITHREADING
++		select SYS_SUPPORTS_SMP
++		select SYS_SUPPORTS_MIPS_CMP
++		select IRQ_GIC
++		select HW_HAS_PCI
++
+ endchoice
+ 
+ choice
+@@ -62,6 +76,10 @@
+ 		bool "MT7620A eval kit"
+ 		depends on SOC_MT7620
+ 
++	config DTB_MT7621_EVAL
++		bool "MT7621 eval kit"
++		depends on SOC_MT7621
++
+ endchoice
+ 
+ endif
+Index: linux-3.10.21/arch/mips/ralink/Makefile
+===================================================================
+--- linux-3.10.21.orig/arch/mips/ralink/Makefile	2013-12-09 19:51:55.600675960 +0100
++++ linux-3.10.21/arch/mips/ralink/Makefile	2013-12-09 19:52:51.756677296 +0100
+@@ -6,7 +6,11 @@
+ # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
+ # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ 
+-obj-y := prom.o of.o reset.o clk.o irq.o timer.o
++obj-y := prom.o of.o reset.o clk.o timer.o
++
++obj-$(CONFIG_IRQ_INTC) += irq.o
++obj-$(CONFIG_IRQ_GIC) += irq-gic.o
++obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
+ 
+ obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
+ 
+@@ -16,6 +20,7 @@
+ obj-$(CONFIG_SOC_RT305X) += rt305x.o
+ obj-$(CONFIG_SOC_RT3883) += rt3883.o
+ obj-$(CONFIG_SOC_MT7620) += mt7620.o
++obj-$(CONFIG_SOC_MT7621) += mt7621.o
+ 
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+ 
+Index: linux-3.10.21/arch/mips/ralink/Platform
+===================================================================
+--- linux-3.10.21.orig/arch/mips/ralink/Platform	2013-12-09 19:51:55.000000000 +0100
++++ linux-3.10.21/arch/mips/ralink/Platform	2013-12-09 19:53:54.660678800 +0100
+@@ -26,3 +26,10 @@
+ # Ralink MT7620
+ #
+ load-$(CONFIG_SOC_MT7620)	+= 0xffffffff80000000
++cflags-$(CONFIG_SOC_MT7620)	+= -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
++
++#
++# Ralink MT7621
++#
++load-$(CONFIG_SOC_MT7621)	+= 0xffffffff80001000
++cflags-$(CONFIG_SOC_MT7620)	+= -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
+Index: linux-3.10.21/arch/mips/ralink/irq-gic.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-3.10.21/arch/mips/ralink/irq-gic.c	2013-12-09 19:52:51.756677296 +0100
+@@ -0,0 +1,255 @@
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/kernel_stat.h>
++#include <linux/hardirq.h>
++#include <linux/preempt.h>
++#include <linux/irqdomain.h>
++#include <linux/of_platform.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++
++#include <asm/irq_cpu.h>
++#include <asm/mipsregs.h>
++
++#include <asm/irq.h>
++#include <asm/setup.h>
++
++#include <asm/gic.h>
++#include <asm/gcmpregs.h>
++
++#include <asm/mach-ralink/mt7621.h>
++
++static unsigned long _gcmp_base;
++static int gic_resched_int_base = 56;
++static int gic_call_int_base = 60;
++static struct irq_chip *irq_gic;
++
++#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
++#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
++
++static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //0
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++	{ GIC_UNUSED },
++        { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //FE
++        { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //PCIE0
++	{ GIC_UNUSED},
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //10
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++	{ GIC_UNUSED },
++	{ GIC_UNUSED },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //20
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++	{ GIC_UNUSED },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //25
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },//30
++        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
++};
++
++static struct gic_intr_map ipi_intr_map[8] = {
++        { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
++        { 1, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
++        { 2, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
++        { 3, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
++        { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
++        { 1, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
++        { 2, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
++        { 3, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
++};
++
++static irqreturn_t
++ipi_resched_interrupt(int irq, void *dev_id)
++{
++	scheduler_ipi();
++
++	return IRQ_HANDLED;
++}
++
++static irqreturn_t
++ipi_call_interrupt(int irq, void *dev_id)
++{
++	smp_call_function_interrupt();
++
++	return IRQ_HANDLED;
++}
++
++static struct irqaction irq_resched = {
++        .handler        = ipi_resched_interrupt,
++        .flags          = IRQF_DISABLED|IRQF_PERCPU,
++        .name           = "ipi resched"
++};
++
++static struct irqaction irq_call = {
++        .handler        = ipi_call_interrupt,
++        .flags          = IRQF_DISABLED|IRQF_PERCPU,
++        .name           = "ipi call"
++};
++
++void
++gic_irq_ack(struct irq_data *d)
++{
++	int irq = (d->irq - gic_irq_base);
++
++	GIC_CLR_INTR_MASK(irq);
++
++	if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
++		GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
++}
++
++void
++gic_finish_irq(struct irq_data *d)
++{
++	GIC_SET_INTR_MASK(d->irq - gic_irq_base);
++}
++
++void __init
++gic_platform_init(int irqs, struct irq_chip *irq_controller)
++{
++	irq_gic = irq_controller;
++}
++
++static void
++vi_gic_irqdispatch(void)
++{
++	int irq = gic_get_int();
++
++	if (irq >= 0)
++		do_IRQ(MIPS_GIC_IRQ_BASE + irq);
++}
++
++static void
++vi_timer_irqdispatch(void)
++{
++	do_IRQ(cp0_compare_irq);
++}
++
++unsigned int
++plat_ipi_call_int_xlate(unsigned int cpu)
++{
++	return GIC_CALL_INT(cpu);
++}
++
++unsigned int
++plat_ipi_resched_int_xlate(unsigned int cpu)
++{
++	return GIC_RESCHED_INT(cpu);
++}
++
++asmlinkage void
++plat_irq_dispatch(void)
++{
++	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
++
++	if (pending & CAUSEF_IP7)
++		do_IRQ(cp0_compare_irq);
++	else if (pending & (CAUSEF_IP4 | CAUSEF_IP3))
++		vi_gic_irqdispatch();
++	else
++		spurious_interrupt();
++}
++
++unsigned int __cpuinit
++get_c0_compare_int(void)
++{
++	return CP0_LEGACY_COMPARE_IRQ;
++}
++
++static int
++gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
++{
++	irq_set_chip_and_handler(irq, irq_gic, handle_percpu_irq);
++
++	return 0;
++}
++
++static const struct irq_domain_ops irq_domain_ops = {
++	.xlate = irq_domain_xlate_onecell,
++	.map = gic_map,
++};
++
++static int __init
++of_gic_init(struct device_node *node,
++				struct device_node *parent)
++{
++	struct irq_domain *domain;
++	struct resource gcmp = { 0 }, gic = { 0 };
++	unsigned int gic_rev;
++	int i;
++
++	if (of_address_to_resource(node, 0, &gic))
++		panic("Failed to get gic memory range");
++	if (request_mem_region(gic.start, resource_size(&gic),
++				gic.name) < 0)
++		panic("Failed to request gic memory");
++	if (of_address_to_resource(node, 2, &gcmp))
++		panic("Failed to get gic memory range");
++	if (request_mem_region(gcmp.start, resource_size(&gcmp),
++				gcmp.name) < 0)
++		panic("Failed to request gcmp memory");
++
++	_gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
++	if (!_gcmp_base)
++		panic("Failed to remap gcmp memory\n");
++
++	if ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) != gcmp.start)
++		panic("Failed to find gcmp core\n");
++
++	/* tell the gcmp where to find the gic */
++	GCMPGCB(GICBA) = gic.start | GCMP_GCB_GICBA_EN_MSK;
++	gic_present = 1;
++	if (cpu_has_vint) {
++		set_vi_handler(3, vi_gic_irqdispatch);
++		set_vi_handler(4, vi_gic_irqdispatch);
++		set_vi_handler(7, vi_timer_irqdispatch);
++	}
++
++	memcpy(&gic_intr_map[gic_resched_int_base], ipi_intr_map, sizeof(ipi_intr_map));
++	gic_init(gic.start, resource_size(&gic), gic_intr_map,
++		ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
++
++	GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
++	pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
++
++	domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
++			0, &irq_domain_ops, NULL);
++	if (!domain)
++		panic("Failed to add irqdomain");
++
++	for (i = 0; i < NR_CPUS; i++) {
++		setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
++		setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
++	}
++
++	change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 |
++				STATUSF_IP7);
++	return 0;
++}
++
++static struct of_device_id __initdata of_irq_ids[] = {
++	{ .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
++	{ .compatible = "ralink,mt7621-gic", .data = of_gic_init },
++	{},
++};
++
++void __init
++arch_init_irq(void)
++{
++	of_irq_init(of_irq_ids);
++}
+Index: linux-3.10.21/arch/mips/ralink/malta-amon.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-3.10.21/arch/mips/ralink/malta-amon.c	2013-12-09 19:52:51.756677296 +0100
+@@ -0,0 +1,81 @@
++/*
++ * Copyright (C) 2007  MIPS Technologies, Inc.
++ *	All rights reserved.
++
++ *  This program is free software; you can distribute it and/or modify it
++ *  under the terms of the GNU General Public License (Version 2) as
++ *  published by the Free Software Foundation.
++ *
++ *  This program is distributed in the hope it will be useful, but WITHOUT
++ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++ *  for more details.
++ *
++ *  You should have received a copy of the GNU General Public License along
++ *  with this program; if not, write to the Free Software Foundation, Inc.,
++ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
++ *
++ * Arbitrary Monitor interface
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/smp.h>
++
++#include <asm/addrspace.h>
++#include <asm/mips-boards/launch.h>
++#include <asm/mipsmtregs.h>
++
++int amon_cpu_avail(int cpu)
++{
++	struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
++
++	if (cpu < 0 || cpu >= NCPULAUNCH) {
++		pr_debug("avail: cpu%d is out of range\n", cpu);
++		return 0;
++	}
++
++	launch += cpu;
++	if (!(launch->flags & LAUNCH_FREADY)) {
++		pr_debug("avail: cpu%d is not ready\n", cpu);
++		return 0;
++	}
++	if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
++		pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
++		return 0;
++	}
++
++	return 1;
++}
++
++void amon_cpu_start(int cpu,
++		    unsigned long pc, unsigned long sp,
++		    unsigned long gp, unsigned long a0)
++{
++	volatile struct cpulaunch *launch =
++		(struct cpulaunch  *)CKSEG0ADDR(CPULAUNCH);
++
++	if (!amon_cpu_avail(cpu))
++		return;
++	if (cpu == smp_processor_id()) {
++		pr_debug("launch: I am cpu%d!\n", cpu);
++		return;
++	}
++	launch += cpu;
++
++	pr_debug("launch: starting cpu%d\n", cpu);
++
++	launch->pc = pc;
++	launch->gp = gp;
++	launch->sp = sp;
++	launch->a0 = a0;
++
++	smp_wmb();		/* Target must see parameters before go */
++	launch->flags |= LAUNCH_FGO;
++	smp_wmb();		/* Target must see go before we poll  */
++
++	while ((launch->flags & LAUNCH_FGONE) == 0)
++		;
++	smp_rmb();	/* Target will be updating flags soon */
++	pr_debug("launch: cpu%d gone!\n", cpu);
++}
+Index: linux-3.10.21/arch/mips/ralink/mt7621.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-3.10.21/arch/mips/ralink/mt7621.c	2013-12-09 19:52:51.760677296 +0100
+@@ -0,0 +1,186 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Parts of this file are based on Ralink's 2.6.21 BSP
++ *
++ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <asm/gcmpregs.h>
++
++#include <asm/mipsregs.h>
++#include <asm/mach-ralink/ralink_regs.h>
++#include <asm/mach-ralink/mt7621.h>
++
++#include <pinmux.h>
++
++#include "common.h"
++
++#define SYSC_REG_SYSCFG		0x10
++#define SYSC_REG_CPLL_CLKCFG0	0x2c
++#define SYSC_REG_CUR_CLK_STS	0x44
++#define CPU_CLK_SEL		(BIT(30) | BIT(31))
++
++#define MT7621_GPIO_MODE_UART1		1
++#define MT7621_GPIO_MODE_I2C		2
++#define MT7621_GPIO_MODE_UART2		3
++#define MT7621_GPIO_MODE_UART3		5
++#define MT7621_GPIO_MODE_JTAG		7
++#define MT7621_GPIO_MODE_WDT_MASK	0x3
++#define MT7621_GPIO_MODE_WDT_SHIFT	8
++#define MT7621_GPIO_MODE_WDT_GPIO	1
++#define MT7621_GPIO_MODE_PCIE_RST	0
++#define MT7621_GPIO_MODE_PCIE_REF	2
++#define MT7621_GPIO_MODE_PCIE_MASK	0x3
++#define MT7621_GPIO_MODE_PCIE_SHIFT	10
++#define MT7621_GPIO_MODE_PCIE_GPIO	1
++#define MT7621_GPIO_MODE_MDIO		12
++#define MT7621_GPIO_MODE_RGMII1		14
++#define MT7621_GPIO_MODE_RGMII2		15
++#define MT7621_GPIO_MODE_SPI_MASK	0x3
++#define MT7621_GPIO_MODE_SPI_SHIFT	16
++#define MT7621_GPIO_MODE_SPI_GPIO	1
++#define MT7621_GPIO_MODE_SDHCI_MASK	0x3
++#define MT7621_GPIO_MODE_SDHCI_SHIFT	18
++#define MT7621_GPIO_MODE_SDHCI_GPIO	1
++
++static struct rt2880_pmx_func uart1_grp[] =  { FUNC("uart1", 0, 1, 2) };
++static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 3, 2) };
++static struct rt2880_pmx_func uart3_grp[] = { FUNC("uart3", 0, 5, 4) };
++static struct rt2880_pmx_func uart2_grp[] = { FUNC("uart2", 0, 9, 4) };
++static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
++static struct rt2880_pmx_func wdt_grp[] = {
++	FUNC("wdt rst", 0, 18, 1),
++	FUNC("wdt refclk", 2, 18, 1),
++};
++static struct rt2880_pmx_func pcie_rst_grp[] = {
++	FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
++	FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
++};
++static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
++static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
++static struct rt2880_pmx_func spi_grp[] = {
++	FUNC("spi", 0, 34, 7),
++	FUNC("nand", 2, 34, 8),
++};
++static struct rt2880_pmx_func sdhci_grp[] = {
++	FUNC("sdhci", 0, 41, 8),
++	FUNC("nand", 2, 41, 8),
++};
++static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
++
++static struct rt2880_pmx_group mt7621_pinmux_data[] = {
++	GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
++	GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
++	GRP("uart3", uart2_grp, 1, MT7621_GPIO_MODE_UART2),
++	GRP("uart2", uart3_grp, 1, MT7621_GPIO_MODE_UART3),
++	GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
++	GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
++		MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
++	GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
++		MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
++	GRP("mdio", mdio_grp, 1, MT7621_GPIO_MODE_MDIO),
++	GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
++	GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
++		MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
++	GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
++		MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
++	GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
++	{ 0 }
++};
++
++void __init ralink_clk_init(void)
++{
++	int cpu_fdiv = 0;
++	int cpu_ffrac = 0;
++	int fbdiv = 0;
++	u32 clk_sts, syscfg;
++	u8 clk_sel = 0, xtal_mode;
++	u32 cpu_clk;
++
++	if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
++		clk_sel = 1;
++
++	switch (clk_sel) {
++	case 0:
++		clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
++		cpu_fdiv = ((clk_sts >> 8) & 0x1F);
++		cpu_ffrac = (clk_sts & 0x1F);
++		cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
++		printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
++		break;
++
++	case 1:
++		fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
++		syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
++		xtal_mode = (syscfg >> 6) & 0x7;
++		printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
++		if(xtal_mode >= 6) { //25Mhz Xtal
++			printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
++			cpu_clk = 25 * fbdiv * 1000 * 1000;
++		} else if(xtal_mode >=3) { //40Mhz Xtal
++			printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
++			cpu_clk = 40 * fbdiv * 1000 * 1000;
++		} else { // 20Mhz Xtal
++			printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
++			cpu_clk = 20 * fbdiv * 1000 * 1000;
++		}
++		break;
++	}
++	cpu_clk = 880000000;
++	ralink_clk_add("cpu", cpu_clk);
++	ralink_clk_add("1e000b00.spi", 50000000);
++	ralink_clk_add("1e000c00.uartlite", 50000000);
++}
++
++void __init ralink_of_remap(void)
++{
++	rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
++	rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
++
++	if (!rt_sysc_membase || !rt_memc_membase)
++		panic("Failed to remap core resources");
++}
++
++void prom_soc_init(struct ralink_soc_info *soc_info)
++{
++	void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
++	unsigned char *name = NULL;
++	u32 n0;
++	u32 n1;
++	u32 rev;
++
++	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
++	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
++
++	if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
++		name = "MT7621";
++		soc_info->compatible = "mtk,mt7621-soc";
++	} else {
++		panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
++	}
++
++	rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
++
++	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
++		"Mediatek %s ver:%u eco:%u",
++		name,
++		(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
++		(rev & CHIP_REV_ECO_MASK));
++
++	soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
++	soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
++	soc_info->mem_base = MT7621_DRAM_BASE;
++
++	rt2880_pinmux_data = mt7621_pinmux_data;
++
++	if (register_cmp_smp_ops())
++		panic("failed to register_vsmp_smp_ops()");
++}
diff --git a/target/linux/ramips/patches-3.10/0503-MIPS-ralink-add-MT7621-early_printk-support.patch b/target/linux/ramips/patches-3.10/0503-MIPS-ralink-add-MT7621-early_printk-support.patch
new file mode 100644
index 0000000000..455fb1d10e
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0503-MIPS-ralink-add-MT7621-early_printk-support.patch
@@ -0,0 +1,39 @@
+From 643e61b22155cd95ae6e18e57da50acd120da091 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 2 Dec 2013 16:11:33 +0100
+Subject: [PATCH 503/507] MIPS: ralink: add MT7621 early_printk support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/early_printk.c |   10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+Index: linux-3.10.21/arch/mips/ralink/early_printk.c
+===================================================================
+--- linux-3.10.21.orig/arch/mips/ralink/early_printk.c	2013-11-29 20:12:03.000000000 +0100
++++ linux-3.10.21/arch/mips/ralink/early_printk.c	2013-12-09 20:11:51.600704498 +0100
+@@ -13,6 +13,8 @@
+ 
+ #ifdef CONFIG_SOC_RT288X
+ #define EARLY_UART_BASE         0x300c00
++#elif defined(CONFIG_SOC_MT7621)
++#define EARLY_UART_BASE         0x1E000c00
+ #else
+ #define EARLY_UART_BASE         0x10000c00
+ #endif
+@@ -40,9 +42,13 @@
+ 
+ void prom_putchar(unsigned char ch)
+ {
+-	while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
++#ifdef CONFIG_SOC_MT7621
++	uart_w32(ch, UART_TX);
++	while ((uart_r32(0x14) & UART_LSR_THRE) == 0)
+ 		;
+-	uart_w32(ch, UART_REG_TX);
++#else
+ 	while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
+ 		;
++	uart_w32(ch, UART_REG_TX);
++#endif
+ }
diff --git a/target/linux/ramips/patches-3.10/0504-MIPS-ralink-add-pcie-driver.patch b/target/linux/ramips/patches-3.10/0504-MIPS-ralink-add-pcie-driver.patch
new file mode 100644
index 0000000000..084a531234
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0504-MIPS-ralink-add-pcie-driver.patch
@@ -0,0 +1,830 @@
+From 50216a5b7b3cc269043e7123db4bea262e35364e Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 2 Dec 2013 16:13:40 +0100
+Subject: [PATCH 504/507] MIPS: ralink: add pcie driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/Makefile     |    1 +
+ arch/mips/pci/pci-mt7621.c |  797 ++++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 798 insertions(+)
+ create mode 100644 arch/mips/pci/pci-mt7621.c
+
+diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
+index 719e455..80886fe 100644
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM)		+= fixup-sni.o ops-sni.o
+ obj-$(CONFIG_LANTIQ)		+= fixup-lantiq.o
+ obj-$(CONFIG_PCI_LANTIQ)	+= pci-lantiq.o ops-lantiq.o
+ obj-$(CONFIG_SOC_RT3883)	+= pci-rt3883.o
++obj-$(CONFIG_SOC_MT7621)	+= pci-mt7621.o
+ obj-$(CONFIG_TANBAC_TB0219)	+= fixup-tb0219.o
+ obj-$(CONFIG_TANBAC_TB0226)	+= fixup-tb0226.o
+ obj-$(CONFIG_TANBAC_TB0287)	+= fixup-tb0287.o
+diff --git a/arch/mips/pci/pci-mt7621.c b/arch/mips/pci/pci-mt7621.c
+new file mode 100644
+index 0000000..0b58fce
+--- /dev/null
++++ b/arch/mips/pci/pci-mt7621.c
+@@ -0,0 +1,797 @@
++/**************************************************************************
++ *
++ *  BRIEF MODULE DESCRIPTION
++ *     PCI init for Ralink RT2880 solution
++ *
++ *  Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
++ *
++ *  This program is free software; you can redistribute  it and/or modify it
++ *  under  the terms of  the GNU General  Public License as published by the
++ *  Free Software Foundation;  either version 2 of the  License, or (at your
++ *  option) any later version.
++ *
++ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
++ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
++ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
++ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
++ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
++ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
++ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
++ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
++ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *  You should have received a copy of the  GNU General Public License along
++ *  with this program; if not, write  to the Free Software Foundation, Inc.,
++ *  675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ *
++ **************************************************************************
++ * May 2007 Bruce Chang
++ * Initial Release
++ *
++ * May 2009 Bruce Chang
++ * support RT2880/RT3883 PCIe
++ *
++ * May 2011 Bruce Chang
++ * support RT6855/MT7620 PCIe
++ *
++ **************************************************************************
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/version.h>
++#include <asm/pci.h>
++#include <asm/io.h>
++//#include <asm/mach-ralink/eureka_ep430.h>
++#include <linux/init.h>
++#include <linux/mod_devicetable.h>
++#include <linux/delay.h>
++//#include <asm/rt2880/surfboardint.h>
++
++#include <ralink_regs.h>
++
++extern void pcie_phy_init(void);
++extern void chk_phy_pll(void);
++
++/*
++ * These functions and structures provide the BIOS scan and mapping of the PCI
++ * devices.
++ */
++
++#define CONFIG_PCIE_PORT0
++#define CONFIG_PCIE_PORT1
++#define CONFIG_PCIE_PORT2
++#define RALINK_PCIE0_CLK_EN             (1<<24)
++#define RALINK_PCIE1_CLK_EN             (1<<25)
++#define RALINK_PCIE2_CLK_EN             (1<<26)
++
++#define RALINK_PCI_CONFIG_ADDR                         0x20
++#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG     0x24
++#define SURFBOARDINT_PCIE0       12      /* PCIE0 */
++#define RALINK_INT_PCIE0         SURFBOARDINT_PCIE0
++#define RALINK_INT_PCIE1         SURFBOARDINT_PCIE1
++#define RALINK_INT_PCIE2         SURFBOARDINT_PCIE2
++#define SURFBOARDINT_PCIE1       32     /* PCIE1 */
++#define SURFBOARDINT_PCIE2       33     /* PCIE2 */
++#define RALINK_PCI_MEMBASE              *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
++#define RALINK_PCI_IOBASE               *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
++#define RALINK_PCIE0_RST                (1<<24)
++#define RALINK_PCIE1_RST                (1<<25)
++#define RALINK_PCIE2_RST                (1<<26)
++#define RALINK_SYSCTL_BASE              0xBE000000
++
++#define RALINK_PCI_PCICFG_ADDR          *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
++#define RALINK_PCI_PCIMSK_ADDR          *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
++#define RALINK_PCI_BASE                 0xBE140000
++
++#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
++#define RT6855_PCIE0_OFFSET     0x2000
++#define RT6855_PCIE1_OFFSET     0x3000
++#define RT6855_PCIE2_OFFSET     0x4000
++
++#define RALINK_PCI0_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
++#define RALINK_PCI0_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
++#define RALINK_PCI0_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
++#define RALINK_PCI0_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
++#define RALINK_PCI0_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
++#define RALINK_PCI0_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
++#define RALINK_PCI0_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
++#define RALINK_PCI0_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
++
++#define RALINK_PCI1_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
++#define RALINK_PCI1_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
++#define RALINK_PCI1_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
++#define RALINK_PCI1_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
++#define RALINK_PCI1_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
++#define RALINK_PCI1_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
++#define RALINK_PCI1_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
++#define RALINK_PCI1_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
++
++#define RALINK_PCI2_BAR0SETUP_ADDR      *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
++#define RALINK_PCI2_IMBASEBAR0_ADDR     *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
++#define RALINK_PCI2_ID                  *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
++#define RALINK_PCI2_CLASS               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
++#define RALINK_PCI2_SUBID               *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
++#define RALINK_PCI2_STATUS              *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
++#define RALINK_PCI2_DERR                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
++#define RALINK_PCI2_ECRC                *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
++
++#define RALINK_PCIEPHY_P0P1_CTL_OFFSET  (RALINK_PCI_BASE + 0x9000)
++#define RALINK_PCIEPHY_P2_CTL_OFFSET    (RALINK_PCI_BASE + 0xA000)
++
++
++#define MV_WRITE(ofs, data)  \
++        *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
++#define MV_READ(ofs, data)   \
++	        *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
++#define MV_READ_DATA(ofs)    \
++		        le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
++
++#define MV_WRITE_16(ofs, data)  \
++        *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
++#define MV_READ_16(ofs, data)   \
++	        *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
++
++#define MV_WRITE_8(ofs, data)  \
++        *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
++#define MV_READ_8(ofs, data)   \
++	        *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
++
++
++
++#define RALINK_PCI_MM_MAP_BASE	0x60000000
++#define RALINK_PCI_IO_MAP_BASE	0x1e160000
++
++#define RALINK_SYSTEM_CONTROL_BASE	0xbe000000
++#define GPIO_PERST
++#define ASSERT_SYSRST_PCIE(val)		do {	\
++						if (*(unsigned int *)(0xbe00000c) == 0x00030101)	\
++							RALINK_RSTCTRL |= val;	\
++						else	\
++							RALINK_RSTCTRL &= ~val;	\
++					} while(0)
++#define DEASSERT_SYSRST_PCIE(val) 	do {	\
++						if (*(unsigned int *)(0xbe00000c) == 0x00030101)	\
++							RALINK_RSTCTRL &= ~val;	\
++						else	\
++							RALINK_RSTCTRL |= val;	\
++					} while(0)
++#define RALINK_SYSCFG1			*(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
++#define RALINK_CLKCFG1			*(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
++#define RALINK_RSTCTRL			*(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
++#define RALINK_GPIOMODE			*(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
++#define RALINK_PCIE_CLK_GEN		*(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
++#define RALINK_PCIE_CLK_GEN1		*(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
++#define PPLL_CFG1			*(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
++#define PPLL_DRV			*(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
++//RALINK_SYSCFG1 bit
++#define RALINK_PCI_HOST_MODE_EN		(1<<7)
++#define RALINK_PCIE_RC_MODE_EN		(1<<8)
++//RALINK_RSTCTRL bit
++#define RALINK_PCIE_RST			(1<<23)
++#define RALINK_PCI_RST			(1<<24)
++//RALINK_CLKCFG1 bit
++#define RALINK_PCI_CLK_EN		(1<<19)
++#define RALINK_PCIE_CLK_EN		(1<<21)
++//RALINK_GPIOMODE bit
++#define PCI_SLOTx2			(1<<11)
++#define PCI_SLOTx1			(2<<11)
++//MTK PCIE PLL bit
++#define PDRV_SW_SET			(1<<31)
++#define LC_CKDRVPD_			(1<<19)
++
++#define MEMORY_BASE 0x0
++int pcie_link_status = 0;
++
++void __inline__ read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val);
++void __inline__ write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val);
++
++#define PCI_ACCESS_READ_1  0
++#define PCI_ACCESS_READ_2  1
++#define PCI_ACCESS_READ_4  2
++#define PCI_ACCESS_WRITE_1 3
++#define PCI_ACCESS_WRITE_2 4
++#define PCI_ACCESS_WRITE_4 5
++
++static int config_access(unsigned char access_type, struct pci_bus *bus,
++			unsigned int devfn, unsigned int where, u32 * data)
++{
++	unsigned int slot = PCI_SLOT(devfn);
++	u8 func = PCI_FUNC(devfn);
++	uint32_t address_reg, data_reg;
++	unsigned int address;
++
++	address_reg = RALINK_PCI_CONFIG_ADDR;
++	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
++
++	address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
++	MV_WRITE(address_reg, address);
++
++	switch(access_type) {
++	case PCI_ACCESS_WRITE_1:
++		MV_WRITE_8(data_reg+(where&0x3), *data);
++		break;
++	case PCI_ACCESS_WRITE_2:
++		MV_WRITE_16(data_reg+(where&0x3), *data);
++		break;
++	case PCI_ACCESS_WRITE_4:
++		MV_WRITE(data_reg, *data);
++		break;
++	case PCI_ACCESS_READ_1:
++		MV_READ_8( data_reg+(where&0x3), data);
++		break;
++	case PCI_ACCESS_READ_2:
++		MV_READ_16(data_reg+(where&0x3), data);
++		break;
++	case PCI_ACCESS_READ_4:
++		MV_READ(data_reg, data);
++		break;
++	default:
++		printk("no specify access type\n");
++		break;
++	}
++	return 0;
++}
++
++static int
++read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
++{
++	return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
++}
++
++static int
++read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
++{
++	return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
++}
++
++static int
++read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
++{
++	return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
++}
++
++static int
++write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
++{
++	if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
++		return -1;
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static int
++write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
++{
++	if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
++		return -1;
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static int
++write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
++{
++	if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
++		return -1;
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++
++static int
++pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
++{
++	switch (size) {
++	case 1:
++		return read_config_byte(bus, devfn, where, (u8 *) val);
++	case 2:
++		return read_config_word(bus, devfn, where, (u16 *) val);
++	default:
++		return read_config_dword(bus, devfn, where, val);
++	}
++}
++
++static int
++pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
++{
++	switch (size) {
++	case 1:
++		return write_config_byte(bus, devfn, where, (u8) val);
++	case 2:
++		return write_config_word(bus, devfn, where, (u16) val);
++	default:
++		return write_config_dword(bus, devfn, where, val);
++	}
++}
++
++struct pci_ops rt2880_pci_ops= {
++	.read		=  pci_config_read,
++	.write		= pci_config_write,
++};
++
++static struct resource rt2880_res_pci_mem1 = {
++	.name		= "PCI MEM1",
++	.start		= RALINK_PCI_MM_MAP_BASE,
++	.end		= (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
++	.flags		= IORESOURCE_MEM,
++};
++static struct resource rt2880_res_pci_io1 = {
++	.name		= "PCI I/O1",
++	.start		= RALINK_PCI_IO_MAP_BASE,
++	.end		= (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
++	.flags		= IORESOURCE_IO,
++};
++
++struct pci_controller rt2880_controller = {
++	.pci_ops	= &rt2880_pci_ops,
++	.mem_resource	= &rt2880_res_pci_mem1,
++	.io_resource	= &rt2880_res_pci_io1,
++	.mem_offset	= 0x00000000UL,
++	.io_offset	= 0x00000000UL,
++	.io_map_base	= 0xa0000000,
++};
++
++void __inline__
++read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
++{
++	unsigned int address_reg, data_reg, address;
++
++	address_reg = RALINK_PCI_CONFIG_ADDR;
++        data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
++	address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
++        MV_WRITE(address_reg, address);
++        MV_READ(data_reg, val);
++	return;
++}
++
++void __inline__
++write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
++{
++	unsigned int address_reg, data_reg, address;
++
++	address_reg = RALINK_PCI_CONFIG_ADDR;
++	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
++	address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
++	MV_WRITE(address_reg, address);
++	MV_WRITE(data_reg, val);
++	return;
++}
++
++
++int __init
++pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++	u16 cmd;
++	u32 val;
++	int irq = 0;
++
++	if ((dev->bus->number == 0) && (slot == 0)) {
++		write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
++		read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
++		printk("BAR0 at slot 0 = %x\n", val);
++		printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++	} else if((dev->bus->number == 0) && (slot == 0x1)) {
++		write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
++		read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
++		printk("BAR0 at slot 1 = %x\n", val);
++		printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++	} else if((dev->bus->number == 0) && (slot == 0x2)) {
++		write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
++		read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
++		printk("BAR0 at slot 2 = %x\n", val);
++		printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++	} else if ((dev->bus->number == 1) && (slot == 0x0)) {
++		switch (pcie_link_status) {
++		case 2:
++		case 6:
++			irq = RALINK_INT_PCIE1;
++			break;
++		case 4:
++			irq = RALINK_INT_PCIE2;
++			break;
++		default:
++			irq = RALINK_INT_PCIE0;
++		}
++		printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++	} else if ((dev->bus->number == 2) && (slot == 0x0)) {
++		switch (pcie_link_status) {
++		case 5:
++		case 6:
++			irq = RALINK_INT_PCIE2;
++			break;
++		default:
++			irq = RALINK_INT_PCIE1;
++		}
++		printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++	} else if ((dev->bus->number == 2) && (slot == 0x1)) {
++		switch (pcie_link_status) {
++		case 5:
++		case 6:
++			irq = RALINK_INT_PCIE2;
++			break;
++		default:
++			irq = RALINK_INT_PCIE1;
++		}
++		printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++	} else if ((dev->bus->number ==3) && (slot == 0x0)) {
++		irq = RALINK_INT_PCIE2;
++		printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++	} else if ((dev->bus->number ==3) && (slot == 0x1)) {
++		irq = RALINK_INT_PCIE2;
++		printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++	} else if ((dev->bus->number ==3) && (slot == 0x2)) {
++		irq = RALINK_INT_PCIE2;
++		printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
++	} else {
++		printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
++		return 0;
++	}
++
++	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
++	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
++	pci_read_config_word(dev, PCI_COMMAND, &cmd);
++	cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
++	pci_write_config_word(dev, PCI_COMMAND, cmd);
++	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
++	return irq;
++}
++
++void
++set_pcie_phy(u32 *addr, int start_b, int bits, int val)
++{
++//	printk("0x%p:", addr);
++//	printk(" %x", *addr);
++	*(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
++	*(unsigned int *)(addr) |= val << start_b;
++//	printk(" -> %x\n", *addr);
++}
++
++void
++bypass_pipe_rst(void)
++{
++#if defined (CONFIG_PCIE_PORT0)
++	/* PCIe Port 0 */
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
++#endif
++#if defined (CONFIG_PCIE_PORT1)
++	/* PCIe Port 1 */
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
++#endif
++#if defined (CONFIG_PCIE_PORT2)
++	/* PCIe Port 2 */
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
++#endif
++}
++
++void
++set_phy_for_ssc(void)
++{
++	unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
++
++	reg = (reg >> 6) & 0x7;
++#if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)
++	/* Set PCIe Port0 & Port1 PHY to disable SSC */
++	/* Debug Xtal Type */
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en               //Force Port 0 enable control
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x01);	// rg_pe1_frc_phy_en               //Force Port 1 enable control
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en                   //Port 0 disable
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x00);	// rg_pe1_phy_en                   //Port 1 disable
++	if(reg <= 5 && reg >= 3) { 	// 40MHz Xtal
++		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
++		printk("***** Xtal 40MHz *****\n");
++	} else {			// 25MHz | 20MHz Xtal
++		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
++		if (reg >= 6) { 	
++			printk("***** Xtal 25MHz *****\n");
++			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL             //Feedback clock select
++			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0,31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO         //DDS NCPO PCW (for host mode)
++			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0,16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD          //DDS SSC dither period control
++			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0,12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA        //DDS SSC dither amplitude control
++			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1       //DDS SSC dither amplitude control for initial
++		} else {
++			printk("***** Xtal 20MHz *****\n");
++		}
++	}
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV         //DDS clock inversion
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC                 
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP                 
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR                 
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC                 
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR                 
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN                
++	if(reg <= 5 && reg >= 3) { 	// 40MHz Xtal
++		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
++		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv          //force mode enable of da_pe1_mstckdiv      
++	}
++	/* Enable PHY and disable force mode */
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en                   //Port 0 enable
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);	// rg_pe1_phy_en                   //Port 1 enable
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en               //Force Port 0 disable control
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);	// rg_pe1_frc_phy_en               //Force Port 1 disable control
++#endif
++#if defined (CONFIG_PCIE_PORT2)
++	/* Set PCIe Port2 PHY to disable SSC */
++	/* Debug Xtal Type */
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en               //Force Port 0 enable control
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en                   //Port 0 disable
++	if(reg <= 5 && reg >= 3) { 	// 40MHz Xtal
++		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
++	} else {			// 25MHz | 20MHz Xtal
++		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV             //Pre-divider ratio (for host mode)
++		if (reg >= 6) { 	// 25MHz Xtal
++			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL             //Feedback clock select
++			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0,31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO         //DDS NCPO PCW (for host mode)
++			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0,16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD          //DDS SSC dither period control
++			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0,12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA        //DDS SSC dither amplitude control
++			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1       //DDS SSC dither amplitude control for initial
++		}
++	}
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV         //DDS clock inversion
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC                 
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP                 
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR                 
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC                 
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR                 
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN                
++	if(reg <= 5 && reg >= 3) { 	// 40MHz Xtal
++		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
++		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv          //force mode enable of da_pe1_mstckdiv      
++	}
++	/* Enable PHY and disable force mode */
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en                   //Port 0 enable
++	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en               //Force Port 0 disable control
++#endif
++}
++
++int init_rt2880pci(void)
++{
++	unsigned long val = 0;
++       iomem_resource.start = 0;
++       iomem_resource.end= ~0;
++       ioport_resource.start= 0;
++       ioport_resource.end = ~0;
++
++#if defined (CONFIG_PCIE_PORT0)
++	val = RALINK_PCIE0_RST;
++#endif
++#if defined (CONFIG_PCIE_PORT1)
++	val |= RALINK_PCIE1_RST;
++#endif
++#if defined (CONFIG_PCIE_PORT2)
++	val |= RALINK_PCIE2_RST;
++#endif
++	DEASSERT_SYSRST_PCIE(val);
++	printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
++
++	bypass_pipe_rst();
++	set_phy_for_ssc();
++	ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
++	printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
++#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
++	*(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
++	*(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
++	mdelay(100);
++	*(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
++	mdelay(100);
++	*(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7);		// clear DATA
++
++	mdelay(100);
++#else
++	*(unsigned int *)(0xbe000060) &= ~0x00000c00;
++#endif
++#if defined (CONFIG_PCIE_PORT0)
++	val = RALINK_PCIE0_RST;
++#endif
++#if defined (CONFIG_PCIE_PORT1)
++	val |= RALINK_PCIE1_RST;
++#endif
++#if defined (CONFIG_PCIE_PORT2)
++	val |= RALINK_PCIE2_RST;
++#endif
++	DEASSERT_SYSRST_PCIE(val);
++	printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
++#if defined (CONFIG_PCIE_PORT0)
++	read_config(0, 0, 0, 0x70c, &val);
++	val &= ~(0xff)<<8;
++	val |= 0x50<<8;
++	write_config(0, 0, 0, 0x70c, val);
++#endif
++#if defined (CONFIG_PCIE_PORT1)
++	read_config(0, 1, 0, 0x70c, &val);
++	val &= ~(0xff)<<8;
++	val |= 0x50<<8;
++	write_config(0, 1, 0, 0x70c, val);
++#endif
++#if defined (CONFIG_PCIE_PORT2)
++	read_config(0, 2, 0, 0x70c, &val);
++	val &= ~(0xff)<<8;
++	val |= 0x50<<8;
++	write_config(0, 2, 0, 0x70c, val);
++#endif
++
++#if defined (CONFIG_PCIE_PORT0)
++	read_config(0, 0, 0, 0x70c, &val);
++	printk("Port 0 N_FTS = %x\n", (unsigned int)val);
++#endif
++#if defined (CONFIG_PCIE_PORT1)
++	read_config(0, 1, 0, 0x70c, &val);
++	printk("Port 1 N_FTS = %x\n", (unsigned int)val);
++#endif
++#if defined (CONFIG_PCIE_PORT2)
++	read_config(0, 2, 0, 0x70c, &val);
++	printk("Port 2 N_FTS = %x\n", (unsigned int)val);
++#endif
++
++	RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
++	RALINK_SYSCFG1 &= ~(0x30);
++	RALINK_SYSCFG1 |= (2<<4);
++	RALINK_PCIE_CLK_GEN &= 0x7fffffff;
++	RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
++	RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
++	RALINK_PCIE_CLK_GEN |= 0x80000000;
++	mdelay(50);
++	RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
++	
++
++#if defined GPIO_PERST /* add GPIO control instead of PERST_N */  /*chhung*/
++	*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;		// set DATA
++	mdelay(100);
++#else
++	RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
++#endif
++	mdelay(500);
++
++
++	mdelay(500);
++#if defined (CONFIG_PCIE_PORT0)
++	if(( RALINK_PCI0_STATUS & 0x1) == 0)
++	{
++		printk("PCIE0 no card, disable it(RST&CLK)\n");
++		ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
++		RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
++		pcie_link_status &= ~(1<<0);
++	} else {
++		pcie_link_status |= 1<<0;
++		RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
++	}
++#endif
++#if defined (CONFIG_PCIE_PORT1)
++	if(( RALINK_PCI1_STATUS & 0x1) == 0)
++	{
++		printk("PCIE1 no card, disable it(RST&CLK)\n");
++		ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
++		RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
++		pcie_link_status &= ~(1<<1);
++	} else {
++		pcie_link_status |= 1<<1;
++		RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
++	}
++#endif
++#if defined (CONFIG_PCIE_PORT2)
++	if (( RALINK_PCI2_STATUS & 0x1) == 0) {
++		printk("PCIE2 no card, disable it(RST&CLK)\n");
++		ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
++		RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
++		pcie_link_status &= ~(1<<2);
++	} else {
++		pcie_link_status |= 1<<2;
++		RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
++	}
++#endif
++	if (pcie_link_status == 0)
++		return 0;
++
++/*
++pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
++3'b000			x		x		x
++3'b001			x		x		0
++3'b010			x		0		x
++3'b011			x		1		0
++3'b100			0		x		x
++3'b101			1		x		0
++3'b110			1		0		x
++3'b111			2		1		0
++*/
++	switch(pcie_link_status) {
++	case 2:
++		RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
++		RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;	//port0
++		RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;	//port1
++		break;
++	case 4:
++		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
++		RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;	//port0
++		RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;	//port1
++		RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;	//port2
++		break;
++	case 5:
++		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
++		RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;	//port0
++		RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;	//port1
++		RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;	//port2
++		break;
++	case 6:
++		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
++		RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;	//port0
++		RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;	//port1
++		RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;	//port2
++		break;
++	}
++	printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
++	//printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
++
++/*
++	ioport_resource.start = rt2880_res_pci_io1.start;
++  	ioport_resource.end = rt2880_res_pci_io1.end;
++*/
++
++	RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
++	RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
++
++#if defined (CONFIG_PCIE_PORT0)
++	//PCIe0
++	if((pcie_link_status & 0x1) != 0) {
++		RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE
++		RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
++		RALINK_PCI0_CLASS = 0x06040001;
++		printk("PCIE0 enabled\n");
++	}
++#endif
++#if defined (CONFIG_PCIE_PORT1)
++	//PCIe1
++	if ((pcie_link_status & 0x2) != 0) {
++		RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE
++		RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
++		RALINK_PCI1_CLASS = 0x06040001;
++		printk("PCIE1 enabled\n");
++	}
++#endif
++#if defined (CONFIG_PCIE_PORT2)
++	//PCIe2
++	if ((pcie_link_status & 0x4) != 0) {
++		RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE
++		RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
++		RALINK_PCI2_CLASS = 0x06040001;
++		printk("PCIE2 enabled\n");
++	}
++#endif
++
++
++	switch(pcie_link_status) {
++	case 7:
++		read_config(0, 2, 0, 0x4, &val);
++		write_config(0, 2, 0, 0x4, val|0x4);
++		// write_config(0, 1, 0, 0x4, val|0x7);
++	case 3:
++	case 5:
++	case 6:
++		read_config(0, 1, 0, 0x4, &val);
++		write_config(0, 1, 0, 0x4, val|0x4);
++		// write_config(0, 1, 0, 0x4, val|0x7);
++	default:
++		read_config(0, 0, 0, 0x4, &val);
++		write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
++		// write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
++	}
++	register_pci_controller(&rt2880_controller);
++	return 0;
++
++}
++arch_initcall(init_rt2880pci);
++
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++	return 0;
++}
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0505-watchdog-add-MT7621-support.patch b/target/linux/ramips/patches-3.10/0505-watchdog-add-MT7621-support.patch
new file mode 100644
index 0000000000..af02f92e25
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0505-watchdog-add-MT7621-support.patch
@@ -0,0 +1,235 @@
+From eb50d97682d78af68388d24956a74de4ab751cf7 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 2 Dec 2013 16:18:36 +0100
+Subject: [PATCH 505/507] watchdog: add MT7621 support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/watchdog/Kconfig      |    7 ++
+ drivers/watchdog/Makefile     |    1 +
+ drivers/watchdog/mt7621_wdt.c |  185 +++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 193 insertions(+)
+ create mode 100644 drivers/watchdog/mt7621_wdt.c
+
+Index: linux-3.10.21/drivers/watchdog/Kconfig
+===================================================================
+--- linux-3.10.21.orig/drivers/watchdog/Kconfig	2013-12-09 19:56:09.360682007 +0100
++++ linux-3.10.21/drivers/watchdog/Kconfig	2013-12-09 19:59:20.636686594 +0100
+@@ -1116,7 +1116,14 @@
+ config RALINK_WDT
+ 	tristate "Ralink SoC watchdog"
+ 	select WATCHDOG_CORE
+-	depends on RALINK
++	depends on RALINK && !SOC_MT7621
++	help
++	  Hardware driver for the Ralink SoC Watchdog Timer.
++
++config MT7621_WDT
++	tristate "Mediatek SoC watchdog"
++	select WATCHDOG_CORE
++	depends on RALINK && SOC_MT7621
+ 	help
+ 	  Hardware driver for the Ralink SoC Watchdog Timer.
+ 
+Index: linux-3.10.21/drivers/watchdog/Makefile
+===================================================================
+--- linux-3.10.21.orig/drivers/watchdog/Makefile	2013-12-09 19:56:09.360682007 +0100
++++ linux-3.10.21/drivers/watchdog/Makefile	2013-12-09 19:56:09.752682016 +0100
+@@ -136,6 +136,7 @@
+ octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
+ obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o
+ obj-$(CONFIG_RALINK_WDT) += rt2880_wdt.o
++obj-$(CONFIG_MT7621_WDT) += mt7621_wdt.o
+ 
+ # PARISC Architecture
+ 
+Index: linux-3.10.21/drivers/watchdog/mt7621_wdt.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-3.10.21/drivers/watchdog/mt7621_wdt.c	2013-12-09 19:56:09.752682016 +0100
+@@ -0,0 +1,185 @@
++/*
++ * Ralink RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
++ *
++ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ *
++ * This driver was based on: drivers/watchdog/softdog.c
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/watchdog.h>
++#include <linux/miscdevice.h>
++#include <linux/moduleparam.h>
++#include <linux/platform_device.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define SYSC_RSTSTAT			0x38
++#define WDT_RST_CAUSE			BIT(1)
++
++#define RALINK_WDT_TIMEOUT		30
++
++#define TIMER_REG_TMRSTAT		0x00
++#define TIMER_REG_TMR1LOAD		0x24
++#define TIMER_REG_TMR1CTL		0x20
++
++#define TMR1CTL_ENABLE			BIT(7)
++#define TMR1CTL_RESTART			BIT(9)
++
++static void __iomem *mt762x_wdt_base;
++
++static bool nowayout = WATCHDOG_NOWAYOUT;
++module_param(nowayout, bool, 0);
++MODULE_PARM_DESC(nowayout,
++		"Watchdog cannot be stopped once started (default="
++		__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
++
++static inline void rt_wdt_w32(unsigned reg, u32 val)
++{
++	iowrite32(val, mt762x_wdt_base + reg);
++}
++
++static inline u32 rt_wdt_r32(unsigned reg)
++{
++	return ioread32(mt762x_wdt_base + reg);
++}
++
++static int mt762x_wdt_ping(struct watchdog_device *w)
++{
++	rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
++
++	return 0;
++}
++
++static int mt762x_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
++{
++	w->timeout = t;
++	rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000);
++	mt762x_wdt_ping(w);
++
++	return 0;
++}
++
++static int mt762x_wdt_start(struct watchdog_device *w)
++{
++	u32 t;
++
++	rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << 16);
++	mt762x_wdt_set_timeout(w, w->timeout);
++
++	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
++	t |= TMR1CTL_ENABLE;
++	rt_wdt_w32(TIMER_REG_TMR1CTL, t);
++
++	return 0;
++}
++
++static int mt762x_wdt_stop(struct watchdog_device *w)
++{
++	u32 t;
++
++	mt762x_wdt_ping(w);
++
++	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
++	t &= ~TMR1CTL_ENABLE;
++	rt_wdt_w32(TIMER_REG_TMR1CTL, t);
++
++	return 0;
++}
++
++static int mt762x_wdt_bootcause(void)
++{
++	if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
++		return WDIOF_CARDRESET;
++
++	return 0;
++}
++
++static struct watchdog_info mt762x_wdt_info = {
++	.identity = "Mediatek Watchdog",
++	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
++};
++
++static struct watchdog_ops mt762x_wdt_ops = {
++	.owner = THIS_MODULE,
++	.start = mt762x_wdt_start,
++	.stop = mt762x_wdt_stop,
++	.ping = mt762x_wdt_ping,
++	.set_timeout = mt762x_wdt_set_timeout,
++};
++
++static struct watchdog_device mt762x_wdt_dev = {
++	.info = &mt762x_wdt_info,
++	.ops = &mt762x_wdt_ops,
++	.min_timeout = 1,
++};
++
++static int mt762x_wdt_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	int ret;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	mt762x_wdt_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (IS_ERR(mt762x_wdt_base))
++		return PTR_ERR(mt762x_wdt_base);
++
++	device_reset(&pdev->dev);
++
++	mt762x_wdt_dev.dev = &pdev->dev;
++	mt762x_wdt_dev.bootstatus = mt762x_wdt_bootcause();
++	mt762x_wdt_dev.max_timeout = (0xfffful / 1000);
++	mt762x_wdt_dev.timeout = mt762x_wdt_dev.max_timeout;
++
++	watchdog_set_nowayout(&mt762x_wdt_dev, nowayout);
++
++	ret = watchdog_register_device(&mt762x_wdt_dev);
++	if (!ret)
++		dev_info(&pdev->dev, "Initialized\n");
++
++	return 0;
++}
++
++static int mt762x_wdt_remove(struct platform_device *pdev)
++{
++	watchdog_unregister_device(&mt762x_wdt_dev);
++
++	return 0;
++}
++
++static void mt762x_wdt_shutdown(struct platform_device *pdev)
++{
++	mt762x_wdt_stop(&mt762x_wdt_dev);
++}
++
++static const struct of_device_id mt762x_wdt_match[] = {
++	{ .compatible = "mtk,mt7621-wdt" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, mt762x_wdt_match);
++
++static struct platform_driver mt762x_wdt_driver = {
++	.probe		= mt762x_wdt_probe,
++	.remove		= mt762x_wdt_remove,
++	.shutdown	= mt762x_wdt_shutdown,
++	.driver		= {
++		.name		= KBUILD_MODNAME,
++		.owner		= THIS_MODULE,
++		.of_match_table	= mt762x_wdt_match,
++	},
++};
++
++module_platform_driver(mt762x_wdt_driver);
++
++MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver");
++MODULE_AUTHOR("John Crispin <blogic@openwrt.org");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
diff --git a/target/linux/ramips/patches-3.10/0506-GPIO-ralink-add-mt7621-gpio-controller.patch b/target/linux/ramips/patches-3.10/0506-GPIO-ralink-add-mt7621-gpio-controller.patch
new file mode 100644
index 0000000000..72048c57cc
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0506-GPIO-ralink-add-mt7621-gpio-controller.patch
@@ -0,0 +1,228 @@
+From e19957560170d63c6a5f0b1d7ba63695e4d1f033 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 2 Dec 2013 16:14:28 +0100
+Subject: [PATCH 506/507] GPIO: ralink: add mt7621 gpio controller
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/Kconfig          |    1 +
+ drivers/gpio/Kconfig       |    6 ++
+ drivers/gpio/Makefile      |    1 +
+ drivers/gpio/gpio-mt7621.c |  183 ++++++++++++++++++++++++++++++++++++++++++++
+ 4 files changed, 191 insertions(+)
+ create mode 100644 drivers/gpio/gpio-mt7621.c
+
+Index: linux-3.10.21/drivers/gpio/Kconfig
+===================================================================
+--- linux-3.10.21.orig/drivers/gpio/Kconfig	2013-12-09 19:56:09.376682007 +0100
++++ linux-3.10.21/drivers/gpio/Kconfig	2013-12-09 19:58:35.372685422 +0100
+@@ -710,6 +710,12 @@
+ 	  Enable support for GPIO on intel MSIC controllers found in
+ 	  intel MID devices
+ 
++config GPIO_MT7621
++	bool "Mediatek GPIO Support"
++	depends on RALINK && SOC_MT7621
++	help
++	  Say yes here to support the Mediatek SoC GPIO device
++
+ comment "USB GPIO expanders:"
+ 
+ config GPIO_VIPERBOARD
+Index: linux-3.10.21/drivers/gpio/Makefile
+===================================================================
+--- linux-3.10.21.orig/drivers/gpio/Makefile	2013-12-09 19:56:09.376682007 +0100
++++ linux-3.10.21/drivers/gpio/Makefile	2013-12-09 19:56:09.760682017 +0100
+@@ -88,3 +88,4 @@
+ obj-$(CONFIG_GPIO_WM8350)	+= gpio-wm8350.o
+ obj-$(CONFIG_GPIO_WM8994)	+= gpio-wm8994.o
+ obj-$(CONFIG_GPIO_XILINX)	+= gpio-xilinx.o
++obj-$(CONFIG_GPIO_MT7621)	+= gpio-mt7621.o
+Index: linux-3.10.21/drivers/gpio/gpio-mt7621.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-3.10.21/drivers/gpio/gpio-mt7621.c	2013-12-09 19:56:09.760682017 +0100
+@@ -0,0 +1,183 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/io.h>
++#include <linux/err.h>
++#include <linux/gpio.h>
++#include <linux/module.h>
++#include <linux/of_irq.h>
++#include <linux/spinlock.h>
++#include <linux/irqdomain.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++
++#define MTK_BANK_WIDTH		32
++
++enum mediatek_gpio_reg {
++	GPIO_REG_CTRL = 0,
++	GPIO_REG_POL,
++	GPIO_REG_DATA,
++	GPIO_REG_DSET,
++	GPIO_REG_DCLR,
++};
++
++static void __iomem *mtk_gc_membase;
++
++struct mtk_gc {
++	struct gpio_chip chip;
++	spinlock_t lock;
++	int bank;
++};
++
++int
++gpio_to_irq(unsigned gpio)
++{
++	return -1;
++}
++
++static inline struct mtk_gc
++*to_mediatek_gpio(struct gpio_chip *chip)
++{
++	struct mtk_gc *mgc;
++
++	mgc = container_of(chip, struct mtk_gc, chip);
++
++	return mgc;
++}
++
++static inline void
++mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val)
++{
++	iowrite32(val, mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
++}
++
++static inline u32
++mtk_gpio_r32(struct mtk_gc *rg, u8 reg)
++{
++	return ioread32(mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
++}
++
++static void
++mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
++{
++	struct mtk_gc *rg = to_mediatek_gpio(chip);
++
++	mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset));
++}
++
++static int
++mediatek_gpio_get(struct gpio_chip *chip, unsigned offset)
++{
++	struct mtk_gc *rg = to_mediatek_gpio(chip);
++
++	return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
++}
++
++static int
++mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
++{
++	struct mtk_gc *rg = to_mediatek_gpio(chip);
++	unsigned long flags;
++	u32 t;
++
++	spin_lock_irqsave(&rg->lock, flags);
++	t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
++	t &= ~BIT(offset);
++	mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
++	spin_unlock_irqrestore(&rg->lock, flags);
++
++	return 0;
++}
++
++static int
++mediatek_gpio_direction_output(struct gpio_chip *chip,
++					unsigned offset, int value)
++{
++	struct mtk_gc *rg = to_mediatek_gpio(chip);
++	unsigned long flags;
++	u32 t;
++
++	spin_lock_irqsave(&rg->lock, flags);
++	t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
++	t |= BIT(offset);
++	mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
++	mediatek_gpio_set(chip, offset, value);
++	spin_unlock_irqrestore(&rg->lock, flags);
++
++	return 0;
++}
++
++static int
++mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
++{
++	const __be32 *id = of_get_property(bank, "reg", NULL);
++	struct mtk_gc *rg = devm_kzalloc(&pdev->dev,
++				sizeof(struct mtk_gc), GFP_KERNEL);
++	if (!rg || !id)
++		return -ENOMEM;
++
++	spin_lock_init(&rg->lock);
++
++	rg->chip.dev = &pdev->dev;
++	rg->chip.label = dev_name(&pdev->dev);
++	rg->chip.of_node = bank;
++	rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id);
++	rg->chip.ngpio = MTK_BANK_WIDTH;
++	rg->chip.direction_input = mediatek_gpio_direction_input;
++	rg->chip.direction_output = mediatek_gpio_direction_output;
++	rg->chip.get = mediatek_gpio_get;
++	rg->chip.set = mediatek_gpio_set;
++
++	/* set polarity to low for all gpios */
++	mtk_gpio_w32(rg, GPIO_REG_POL, 0);
++
++	dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
++
++	return gpiochip_add(&rg->chip);
++}
++
++static int
++mediatek_gpio_probe(struct platform_device *pdev)
++{
++	struct device_node *bank, *np = pdev->dev.of_node;
++	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++	mtk_gc_membase = devm_request_and_ioremap(&pdev->dev, res);
++	if (IS_ERR(mtk_gc_membase))
++		return PTR_ERR(mtk_gc_membase);
++
++	for_each_child_of_node(np, bank)
++		if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank"))
++			mediatek_gpio_bank_probe(pdev, bank);
++
++	return 0;
++}
++
++static const struct of_device_id mediatek_gpio_match[] = {
++	{ .compatible = "mtk,mt7621-gpio" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
++
++static struct platform_driver mediatek_gpio_driver = {
++	.probe = mediatek_gpio_probe,
++	.driver = {
++		.name = "mt7621_gpio",
++		.owner = THIS_MODULE,
++		.of_match_table = mediatek_gpio_match,
++	},
++};
++
++static int __init
++mediatek_gpio_init(void)
++{
++	return platform_driver_register(&mediatek_gpio_driver);
++}
++
++subsys_initcall(mediatek_gpio_init);
diff --git a/target/linux/ramips/patches-3.10/0507-MTD-add-mt7621-nand-support.patch b/target/linux/ramips/patches-3.10/0507-MTD-add-mt7621-nand-support.patch
new file mode 100644
index 0000000000..6a1478207f
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0507-MTD-add-mt7621-nand-support.patch
@@ -0,0 +1,4456 @@
+From 203189714320fe43b4c0cf953efec9e28963c03b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 2 Dec 2013 16:23:57 +0100
+Subject: [PATCH 507/507] MTD: add mt7621 nand support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/nand/Kconfig            |    6 +
+ drivers/mtd/nand/Makefile           |    1 +
+ drivers/mtd/nand/bmt.c              |  750 ++++++++++++
+ drivers/mtd/nand/bmt.h              |   80 ++
+ drivers/mtd/nand/dev-nand.c         |   63 +
+ drivers/mtd/nand/mt6575_typedefs.h  |  340 ++++++
+ drivers/mtd/nand/mtk_nand.c         | 2304 +++++++++++++++++++++++++++++++++++
+ drivers/mtd/nand/mtk_nand.h         |  452 +++++++
+ drivers/mtd/nand/nand_base.c        |    6 +-
+ drivers/mtd/nand/nand_bbt.c         |   19 +
+ drivers/mtd/nand/nand_def.h         |  123 ++
+ drivers/mtd/nand/nand_device_list.h |   55 +
+ drivers/mtd/nand/partition.h        |  115 ++
+ 13 files changed, 4311 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/mtd/nand/bmt.c
+ create mode 100644 drivers/mtd/nand/bmt.h
+ create mode 100644 drivers/mtd/nand/dev-nand.c
+ create mode 100644 drivers/mtd/nand/mt6575_typedefs.h
+ create mode 100644 drivers/mtd/nand/mtk_nand.c
+ create mode 100644 drivers/mtd/nand/mtk_nand.h
+ create mode 100644 drivers/mtd/nand/nand_def.h
+ create mode 100644 drivers/mtd/nand/nand_device_list.h
+ create mode 100644 drivers/mtd/nand/partition.h
+
+diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
+index d885298..51ba744 100644
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -538,4 +538,10 @@ config MTD_NAND_XWAY
+ 	  Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
+ 	  to the External Bus Unit (EBU).
+ 
++config MTK_MTD_NAND
++	tristate "Support for MTK SoC NAND controller"
++	depends on SOC_MT7621
++	select MTD_NAND_IDS
++	select MTD_NAND_ECC
++
+ endif # MTD_NAND
+diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
+index 542b568..c68c96c 100644
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -49,5 +49,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740)		+= jz4740_nand.o
+ obj-$(CONFIG_MTD_NAND_GPMI_NAND)	+= gpmi-nand/
+ obj-$(CONFIG_MTD_NAND_XWAY)		+= xway_nand.o
+ obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash/
++obj-$(CONFIG_MTK_MTD_NAND)                      += mtk_nand.o bmt.o
+ 
+ nand-objs := nand_base.o nand_bbt.o
+diff --git a/drivers/mtd/nand/bmt.c b/drivers/mtd/nand/bmt.c
+new file mode 100644
+index 0000000..0462871
+--- /dev/null
++++ b/drivers/mtd/nand/bmt.c
+@@ -0,0 +1,750 @@
++#include "bmt.h"
++
++typedef struct
++{
++    char signature[3];
++    u8 version;
++    u8 bad_count;               // bad block count in pool
++    u8 mapped_count;            // mapped block count in pool
++    u8 checksum;
++    u8 reseverd[13];
++} phys_bmt_header;
++
++typedef struct
++{
++    phys_bmt_header header;
++    bmt_entry table[MAX_BMT_SIZE];
++} phys_bmt_struct;
++
++typedef struct
++{
++    char signature[3];
++} bmt_oob_data;
++
++static char MAIN_SIGNATURE[] = "BMT";
++static char OOB_SIGNATURE[] = "bmt";
++#define SIGNATURE_SIZE      (3)
++
++#define MAX_DAT_SIZE        0x1000
++#define MAX_OOB_SIZE        0x80
++
++static struct mtd_info *mtd_bmt;
++static struct nand_chip *nand_chip_bmt;
++#define BLOCK_SIZE_BMT          (1 << nand_chip_bmt->phys_erase_shift)
++#define PAGE_SIZE_BMT           (1 << nand_chip_bmt->page_shift)
++
++#define OFFSET(block)       ((block) * BLOCK_SIZE_BMT)  
++#define PAGE_ADDR(block)    ((block) * BLOCK_SIZE_BMT / PAGE_SIZE_BMT)
++
++/*********************************************************************
++* Flash is splited into 2 parts, system part is for normal system    *
++* system usage, size is system_block_count, another is replace pool  *
++*    +-------------------------------------------------+             *
++*    |     system_block_count     |   bmt_block_count  |             *
++*    +-------------------------------------------------+             *
++*********************************************************************/
++static u32 total_block_count;   // block number in flash
++static u32 system_block_count;
++static int bmt_block_count;     // bmt table size
++// static int bmt_count;               // block used in bmt
++static int page_per_block;      // page per count
++
++static u32 bmt_block_index;     // bmt block index
++static bmt_struct bmt;          // dynamic created global bmt table
++
++static u8 dat_buf[MAX_DAT_SIZE];
++static u8 oob_buf[MAX_OOB_SIZE];
++static bool pool_erased;
++
++/***************************************************************
++*                                                              
++* Interface adaptor for preloader/uboot/kernel                 
++*    These interfaces operate on physical address, read/write
++*       physical data.
++*                                                              
++***************************************************************/
++int nand_read_page_bmt(u32 page, u8 * dat, u8 * oob)
++{
++    return mtk_nand_exec_read_page(mtd_bmt, page, PAGE_SIZE_BMT, dat, oob);
++}
++
++bool nand_block_bad_bmt(u32 offset)
++{
++    return mtk_nand_block_bad_hw(mtd_bmt, offset);
++}
++
++bool nand_erase_bmt(u32 offset)
++{
++    int status;
++    if (offset < 0x20000)
++    {
++        MSG(INIT, "erase offset: 0x%x\n", offset);
++    }
++
++    status = mtk_nand_erase_hw(mtd_bmt, offset / PAGE_SIZE_BMT); // as nand_chip structure doesn't have a erase function defined
++    if (status & NAND_STATUS_FAIL)
++        return false;
++    else
++        return true;
++}
++
++int mark_block_bad_bmt(u32 offset)
++{
++    return mtk_nand_block_markbad_hw(mtd_bmt, offset);   //mark_block_bad_hw(offset);
++}
++
++bool nand_write_page_bmt(u32 page, u8 * dat, u8 * oob)
++{
++    if (mtk_nand_exec_write_page(mtd_bmt, page, PAGE_SIZE_BMT, dat, oob))
++        return false;
++    else
++        return true;
++}
++
++/***************************************************************
++*                                                              *
++* static internal function                                     *
++*                                                              *
++***************************************************************/
++static void dump_bmt_info(bmt_struct * bmt)
++{
++    int i;
++
++    MSG(INIT, "BMT v%d. total %d mapping:\n", bmt->version, bmt->mapped_count);
++    for (i = 0; i < bmt->mapped_count; i++)
++    {
++        MSG(INIT, "\t0x%x -> 0x%x\n", bmt->table[i].bad_index, bmt->table[i].mapped_index);
++    }
++}
++
++static bool match_bmt_signature(u8 * dat, u8 * oob)
++{
++
++    if (memcmp(dat + MAIN_SIGNATURE_OFFSET, MAIN_SIGNATURE, SIGNATURE_SIZE))
++    {
++        return false;
++    }
++
++    if (memcmp(oob + OOB_SIGNATURE_OFFSET, OOB_SIGNATURE, SIGNATURE_SIZE))
++    {
++        MSG(INIT, "main signature match, oob signature doesn't match, but ignore\n");
++    }
++    return true;
++}
++
++static u8 cal_bmt_checksum(phys_bmt_struct * phys_table, int bmt_size)
++{
++    int i;
++    u8 checksum = 0;
++    u8 *dat = (u8 *) phys_table;
++
++    checksum += phys_table->header.version;
++    checksum += phys_table->header.mapped_count;
++
++    dat += sizeof(phys_bmt_header);
++    for (i = 0; i < bmt_size * sizeof(bmt_entry); i++)
++    {
++        checksum += dat[i];
++    }
++
++    return checksum;
++}
++
++
++static int is_block_mapped(int index)
++{
++    int i;
++    for (i = 0; i < bmt.mapped_count; i++)
++    {
++        if (index == bmt.table[i].mapped_index)
++            return i;
++    }
++    return -1;
++}
++
++static bool is_page_used(u8 * dat, u8 * oob)
++{
++    return ((oob[OOB_INDEX_OFFSET] != 0xFF) || (oob[OOB_INDEX_OFFSET + 1] != 0xFF));
++}
++
++static bool valid_bmt_data(phys_bmt_struct * phys_table)
++{
++    int i;
++    u8 checksum = cal_bmt_checksum(phys_table, bmt_block_count);
++
++    // checksum correct?
++    if (phys_table->header.checksum != checksum)
++    {
++        MSG(INIT, "BMT Data checksum error: %x %x\n", phys_table->header.checksum, checksum);
++        return false;
++    }
++
++    MSG(INIT, "BMT Checksum is: 0x%x\n", phys_table->header.checksum);
++
++    // block index correct?
++    for (i = 0; i < phys_table->header.mapped_count; i++)
++    {
++        if (phys_table->table[i].bad_index >= total_block_count || phys_table->table[i].mapped_index >= total_block_count || phys_table->table[i].mapped_index < system_block_count)
++        {
++            MSG(INIT, "index error: bad_index: %d, mapped_index: %d\n", phys_table->table[i].bad_index, phys_table->table[i].mapped_index);
++            return false;
++        }
++    }
++
++    // pass check, valid bmt.
++    MSG(INIT, "Valid BMT, version v%d\n", phys_table->header.version);
++    return true;
++}
++
++static void fill_nand_bmt_buffer(bmt_struct * bmt, u8 * dat, u8 * oob)
++{
++    phys_bmt_struct phys_bmt;
++
++    dump_bmt_info(bmt);
++
++    // fill phys_bmt_struct structure with bmt_struct
++    memset(&phys_bmt, 0xFF, sizeof(phys_bmt));
++
++    memcpy(phys_bmt.header.signature, MAIN_SIGNATURE, SIGNATURE_SIZE);
++    phys_bmt.header.version = BMT_VERSION;
++    // phys_bmt.header.bad_count = bmt->bad_count;
++    phys_bmt.header.mapped_count = bmt->mapped_count;
++    memcpy(phys_bmt.table, bmt->table, sizeof(bmt_entry) * bmt_block_count);
++
++    phys_bmt.header.checksum = cal_bmt_checksum(&phys_bmt, bmt_block_count);
++
++    memcpy(dat + MAIN_SIGNATURE_OFFSET, &phys_bmt, sizeof(phys_bmt));
++    memcpy(oob + OOB_SIGNATURE_OFFSET, OOB_SIGNATURE, SIGNATURE_SIZE);
++}
++
++// return valid index if found BMT, else return 0
++static int load_bmt_data(int start, int pool_size)
++{
++    int bmt_index = start + pool_size - 1;  // find from the end
++    phys_bmt_struct phys_table;
++    int i;
++
++    MSG(INIT, "[%s]: begin to search BMT from block 0x%x\n", __FUNCTION__, bmt_index);
++
++    for (bmt_index = start + pool_size - 1; bmt_index >= start; bmt_index--)
++    {
++        if (nand_block_bad_bmt(OFFSET(bmt_index)))
++        {
++            MSG(INIT, "Skip bad block: %d\n", bmt_index);
++            continue;
++        }
++
++        if (!nand_read_page_bmt(PAGE_ADDR(bmt_index), dat_buf, oob_buf))
++        {
++            MSG(INIT, "Error found when read block %d\n", bmt_index);
++            continue;
++        }
++
++        if (!match_bmt_signature(dat_buf, oob_buf))
++        {
++            continue;
++        }
++
++        MSG(INIT, "Match bmt signature @ block: 0x%x\n", bmt_index);
++
++        memcpy(&phys_table, dat_buf + MAIN_SIGNATURE_OFFSET, sizeof(phys_table));
++
++        if (!valid_bmt_data(&phys_table))
++        {
++            MSG(INIT, "BMT data is not correct %d\n", bmt_index);
++            continue;
++        } else
++        {
++            bmt.mapped_count = phys_table.header.mapped_count;
++            bmt.version = phys_table.header.version;
++            // bmt.bad_count = phys_table.header.bad_count;
++            memcpy(bmt.table, phys_table.table, bmt.mapped_count * sizeof(bmt_entry));
++
++            MSG(INIT, "bmt found at block: %d, mapped block: %d\n", bmt_index, bmt.mapped_count);
++
++            for (i = 0; i < bmt.mapped_count; i++)
++            {
++                if (!nand_block_bad_bmt(OFFSET(bmt.table[i].bad_index)))
++                {
++                    MSG(INIT, "block 0x%x is not mark bad, should be power lost last time\n", bmt.table[i].bad_index);
++                    mark_block_bad_bmt(OFFSET(bmt.table[i].bad_index));
++                }
++            }
++
++            return bmt_index;
++        }
++    }
++
++    MSG(INIT, "bmt block not found!\n");
++    return 0;
++}
++
++/*************************************************************************
++* Find an available block and erase.                                     *
++* start_from_end: if true, find available block from end of flash.       *
++*                 else, find from the beginning of the pool              *
++* need_erase: if true, all unmapped blocks in the pool will be erased    *
++*************************************************************************/
++static int find_available_block(bool start_from_end)
++{
++    int i;                      // , j;
++    int block = system_block_count;
++    int direction;
++    // int avail_index = 0;
++    MSG(INIT, "Try to find_available_block, pool_erase: %d\n", pool_erased);
++
++    // erase all un-mapped blocks in pool when finding avaliable block
++    if (!pool_erased)
++    {
++        MSG(INIT, "Erase all un-mapped blocks in pool\n");
++        for (i = 0; i < bmt_block_count; i++)
++        {
++            if (block == bmt_block_index)
++            {
++                MSG(INIT, "Skip bmt block 0x%x\n", block);
++                continue;
++            }
++
++            if (nand_block_bad_bmt(OFFSET(block + i)))
++            {
++                MSG(INIT, "Skip bad block 0x%x\n", block + i);
++                continue;
++            }
++//if(block==4095)
++//{
++//  continue;
++//}
++
++            if (is_block_mapped(block + i) >= 0)
++            {
++                MSG(INIT, "Skip mapped block 0x%x\n", block + i);
++                continue;
++            }
++
++            if (!nand_erase_bmt(OFFSET(block + i)))
++            {
++                MSG(INIT, "Erase block 0x%x failed\n", block + i);
++                mark_block_bad_bmt(OFFSET(block + i));
++            }
++        }
++
++        pool_erased = 1;
++    }
++
++    if (start_from_end)
++    {
++        block = total_block_count - 1;
++        direction = -1;
++    } else
++    {
++        block = system_block_count;
++        direction = 1;
++    }
++
++    for (i = 0; i < bmt_block_count; i++, block += direction)
++    {
++        if (block == bmt_block_index)
++        {
++            MSG(INIT, "Skip bmt block 0x%x\n", block);
++            continue;
++        }
++
++        if (nand_block_bad_bmt(OFFSET(block)))
++        {
++            MSG(INIT, "Skip bad block 0x%x\n", block);
++            continue;
++        }
++
++        if (is_block_mapped(block) >= 0)
++        {
++            MSG(INIT, "Skip mapped block 0x%x\n", block);
++            continue;
++        }
++
++        MSG(INIT, "Find block 0x%x available\n", block);
++        return block;
++    }
++
++    return 0;
++}
++
++static unsigned short get_bad_index_from_oob(u8 * oob_buf)
++{
++    unsigned short index;
++    memcpy(&index, oob_buf + OOB_INDEX_OFFSET, OOB_INDEX_SIZE);
++
++    return index;
++}
++
++void set_bad_index_to_oob(u8 * oob, u16 index)
++{
++    memcpy(oob + OOB_INDEX_OFFSET, &index, sizeof(index));
++}
++
++static int migrate_from_bad(int offset, u8 * write_dat, u8 * write_oob)
++{
++    int page;
++    int error_block = offset / BLOCK_SIZE_BMT;
++    int error_page = (offset / PAGE_SIZE_BMT) % page_per_block;
++    int to_index;
++
++    memcpy(oob_buf, write_oob, MAX_OOB_SIZE);
++
++    to_index = find_available_block(false);
++
++    if (!to_index)
++    {
++        MSG(INIT, "Cannot find an available block for BMT\n");
++        return 0;
++    }
++
++    {                           // migrate error page first
++        MSG(INIT, "Write error page: 0x%x\n", error_page);
++        if (!write_dat)
++        {
++            nand_read_page_bmt(PAGE_ADDR(error_block) + error_page, dat_buf, NULL);
++            write_dat = dat_buf;
++        }
++        // memcpy(oob_buf, write_oob, MAX_OOB_SIZE);
++
++        if (error_block < system_block_count)
++            set_bad_index_to_oob(oob_buf, error_block); // if error_block is already a mapped block, original mapping index is in OOB.
++
++        if (!nand_write_page_bmt(PAGE_ADDR(to_index) + error_page, write_dat, oob_buf))
++        {
++            MSG(INIT, "Write to page 0x%x fail\n", PAGE_ADDR(to_index) + error_page);
++            mark_block_bad_bmt(to_index);
++            return migrate_from_bad(offset, write_dat, write_oob);
++        }
++    }
++
++    for (page = 0; page < page_per_block; page++)
++    {
++        if (page != error_page)
++        {
++            nand_read_page_bmt(PAGE_ADDR(error_block) + page, dat_buf, oob_buf);
++            if (is_page_used(dat_buf, oob_buf))
++            {
++                if (error_block < system_block_count)
++                {
++                    set_bad_index_to_oob(oob_buf, error_block);
++                }
++                MSG(INIT, "\tmigrate page 0x%x to page 0x%x\n", PAGE_ADDR(error_block) + page, PAGE_ADDR(to_index) + page);
++                if (!nand_write_page_bmt(PAGE_ADDR(to_index) + page, dat_buf, oob_buf))
++                {
++                    MSG(INIT, "Write to page 0x%x fail\n", PAGE_ADDR(to_index) + page);
++                    mark_block_bad_bmt(to_index);
++                    return migrate_from_bad(offset, write_dat, write_oob);
++                }
++            }
++        }
++    }
++
++    MSG(INIT, "Migrate from 0x%x to 0x%x done!\n", error_block, to_index);
++
++    return to_index;
++}
++
++static bool write_bmt_to_flash(u8 * dat, u8 * oob)
++{
++    bool need_erase = true;
++    MSG(INIT, "Try to write BMT\n");
++
++    if (bmt_block_index == 0)
++    {
++        // if we don't have index, we don't need to erase found block as it has been erased in find_available_block()
++        need_erase = false;
++        if (!(bmt_block_index = find_available_block(true)))
++        {
++            MSG(INIT, "Cannot find an available block for BMT\n");
++            return false;
++        }
++    }
++
++    MSG(INIT, "Find BMT block: 0x%x\n", bmt_block_index);
++
++    // write bmt to flash
++    if (need_erase)
++    {
++        if (!nand_erase_bmt(OFFSET(bmt_block_index)))
++        {
++            MSG(INIT, "BMT block erase fail, mark bad: 0x%x\n", bmt_block_index);
++            mark_block_bad_bmt(OFFSET(bmt_block_index));
++            // bmt.bad_count++;
++
++            bmt_block_index = 0;
++            return write_bmt_to_flash(dat, oob);    // recursive call 
++        }
++    }
++
++    if (!nand_write_page_bmt(PAGE_ADDR(bmt_block_index), dat, oob))
++    {
++        MSG(INIT, "Write BMT data fail, need to write again\n");
++        mark_block_bad_bmt(OFFSET(bmt_block_index));
++        // bmt.bad_count++;
++
++        bmt_block_index = 0;
++        return write_bmt_to_flash(dat, oob);    // recursive call 
++    }
++
++    MSG(INIT, "Write BMT data to block 0x%x success\n", bmt_block_index);
++    return true;
++}
++
++/*******************************************************************
++* Reconstruct bmt, called when found bmt info doesn't match bad 
++* block info in flash.
++* 
++* Return NULL for failure
++*******************************************************************/
++bmt_struct *reconstruct_bmt(bmt_struct * bmt)
++{
++    int i;
++    int index = system_block_count;
++    unsigned short bad_index;
++    int mapped;
++
++    // init everything in BMT struct 
++    bmt->version = BMT_VERSION;
++    bmt->bad_count = 0;
++    bmt->mapped_count = 0;
++
++    memset(bmt->table, 0, bmt_block_count * sizeof(bmt_entry));
++
++    for (i = 0; i < bmt_block_count; i++, index++)
++    {
++        if (nand_block_bad_bmt(OFFSET(index)))
++        {
++            MSG(INIT, "Skip bad block: 0x%x\n", index);
++            // bmt->bad_count++;
++            continue;
++        }
++
++        MSG(INIT, "read page: 0x%x\n", PAGE_ADDR(index));
++        nand_read_page_bmt(PAGE_ADDR(index), dat_buf, oob_buf);
++        /* if (mtk_nand_read_page_hw(PAGE_ADDR(index), dat_buf))
++           {
++           MSG(INIT,  "Error when read block %d\n", bmt_block_index);
++           continue;
++           } */
++
++        if ((bad_index = get_bad_index_from_oob(oob_buf)) >= system_block_count)
++        {
++            MSG(INIT, "get bad index: 0x%x\n", bad_index);
++            if (bad_index != 0xFFFF)
++                MSG(INIT, "Invalid bad index found in block 0x%x, bad index 0x%x\n", index, bad_index);
++            continue;
++        }
++
++        MSG(INIT, "Block 0x%x is mapped to bad block: 0x%x\n", index, bad_index);
++
++        if (!nand_block_bad_bmt(OFFSET(bad_index)))
++        {
++            MSG(INIT, "\tbut block 0x%x is not marked as bad, invalid mapping\n", bad_index);
++            continue;           // no need to erase here, it will be erased later when trying to write BMT
++        }
++
++        if ((mapped = is_block_mapped(bad_index)) >= 0)
++        {
++            MSG(INIT, "bad block 0x%x is mapped to 0x%x, should be caused by power lost, replace with one\n", bmt->table[mapped].bad_index, bmt->table[mapped].mapped_index);
++            bmt->table[mapped].mapped_index = index;    // use new one instead.
++        } else
++        {
++            // add mapping to BMT
++            bmt->table[bmt->mapped_count].bad_index = bad_index;
++            bmt->table[bmt->mapped_count].mapped_index = index;
++            bmt->mapped_count++;
++        }
++
++        MSG(INIT, "Add mapping: 0x%x -> 0x%x to BMT\n", bad_index, index);
++
++    }
++
++    MSG(INIT, "Scan replace pool done, mapped block: %d\n", bmt->mapped_count);
++    // dump_bmt_info(bmt);
++
++    // fill NAND BMT buffer
++    memset(oob_buf, 0xFF, sizeof(oob_buf));
++    fill_nand_bmt_buffer(bmt, dat_buf, oob_buf);
++
++    // write BMT back
++    if (!write_bmt_to_flash(dat_buf, oob_buf))
++    {
++        MSG(INIT, "TRAGEDY: cannot find a place to write BMT!!!!\n");
++    }
++
++    return bmt;
++}
++
++/*******************************************************************
++* [BMT Interface]
++*
++* Description:
++*   Init bmt from nand. Reconstruct if not found or data error
++*
++* Parameter:
++*   size: size of bmt and replace pool
++* 
++* Return: 
++*   NULL for failure, and a bmt struct for success
++*******************************************************************/
++bmt_struct *init_bmt(struct nand_chip * chip, int size)
++{
++    struct mtk_nand_host *host;
++
++    if (size > 0 && size < MAX_BMT_SIZE)
++    {
++        MSG(INIT, "Init bmt table, size: %d\n", size);
++        bmt_block_count = size;
++    } else
++    {
++        MSG(INIT, "Invalid bmt table size: %d\n", size);
++        return NULL;
++    }
++    nand_chip_bmt = chip;
++    system_block_count = chip->chipsize >> chip->phys_erase_shift;
++    total_block_count = bmt_block_count + system_block_count;
++    page_per_block = BLOCK_SIZE_BMT / PAGE_SIZE_BMT;
++    host = (struct mtk_nand_host *)chip->priv;
++    mtd_bmt = &host->mtd;
++
++    MSG(INIT, "mtd_bmt: %p, nand_chip_bmt: %p\n", mtd_bmt, nand_chip_bmt);
++    MSG(INIT, "bmt count: %d, system count: %d\n", bmt_block_count, system_block_count);
++
++    // set this flag, and unmapped block in pool will be erased.
++    pool_erased = 0;
++    memset(bmt.table, 0, size * sizeof(bmt_entry));
++    if ((bmt_block_index = load_bmt_data(system_block_count, size)))
++    {
++        MSG(INIT, "Load bmt data success @ block 0x%x\n", bmt_block_index);
++        dump_bmt_info(&bmt);
++        return &bmt;
++    } else
++    {
++        MSG(INIT, "Load bmt data fail, need re-construct!\n");
++#ifndef __UBOOT_NAND__            // BMT is not re-constructed in UBOOT.
++        if (reconstruct_bmt(&bmt))
++            return &bmt;
++        else
++#endif
++            return NULL;
++    }
++}
++
++/*******************************************************************
++* [BMT Interface]
++*
++* Description:
++*   Update BMT.
++*
++* Parameter:
++*   offset: update block/page offset.
++*   reason: update reason, see update_reason_t for reason.
++*   dat/oob: data and oob buffer for write fail.
++* 
++* Return: 
++*   Return true for success, and false for failure.
++*******************************************************************/
++bool update_bmt(u32 offset, update_reason_t reason, u8 * dat, u8 * oob)
++{
++    int map_index;
++    int orig_bad_block = -1;
++    // int bmt_update_index;
++    int i;
++    int bad_index = offset / BLOCK_SIZE_BMT;
++
++#ifndef MTK_NAND_BMT
++	return false;
++#endif
++    if (reason == UPDATE_WRITE_FAIL)
++    {
++        MSG(INIT, "Write fail, need to migrate\n");
++        if (!(map_index = migrate_from_bad(offset, dat, oob)))
++        {
++            MSG(INIT, "migrate fail\n");
++            return false;
++        }
++    } else
++    {
++        if (!(map_index = find_available_block(false)))
++        {
++            MSG(INIT, "Cannot find block in pool\n");
++            return false;
++        }
++    }
++
++    // now let's update BMT
++    if (bad_index >= system_block_count)    // mapped block become bad, find original bad block
++    {
++        for (i = 0; i < bmt_block_count; i++)
++        {
++            if (bmt.table[i].mapped_index == bad_index)
++            {
++                orig_bad_block = bmt.table[i].bad_index;
++                break;
++            }
++        }
++        // bmt.bad_count++;
++        MSG(INIT, "Mapped block becomes bad, orig bad block is 0x%x\n", orig_bad_block);
++
++        bmt.table[i].mapped_index = map_index;
++    } else
++    {
++        bmt.table[bmt.mapped_count].mapped_index = map_index;
++        bmt.table[bmt.mapped_count].bad_index = bad_index;
++        bmt.mapped_count++;
++    }
++
++    memset(oob_buf, 0xFF, sizeof(oob_buf));
++    fill_nand_bmt_buffer(&bmt, dat_buf, oob_buf);
++    if (!write_bmt_to_flash(dat_buf, oob_buf))
++        return false;
++
++    mark_block_bad_bmt(offset);
++
++    return true;
++}
++
++/*******************************************************************
++* [BMT Interface]
++*
++* Description:
++*   Given an block index, return mapped index if it's mapped, else 
++*   return given index.
++*
++* Parameter:
++*   index: given an block index. This value cannot exceed 
++*   system_block_count.
++*
++* Return NULL for failure
++*******************************************************************/
++u16 get_mapping_block_index(int index)
++{
++    int i;
++#ifndef MTK_NAND_BMT
++	return index;
++#endif
++    if (index > system_block_count)
++    {
++        return index;
++    }
++
++    for (i = 0; i < bmt.mapped_count; i++)
++    {
++        if (bmt.table[i].bad_index == index)
++        {
++            return bmt.table[i].mapped_index;
++        }
++    }
++
++    return index;
++}
++#ifdef __KERNEL_NAND__
++EXPORT_SYMBOL_GPL(init_bmt);
++EXPORT_SYMBOL_GPL(update_bmt);
++EXPORT_SYMBOL_GPL(get_mapping_block_index);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("MediaTek");
++MODULE_DESCRIPTION("Bad Block mapping management for MediaTek NAND Flash Driver");
++#endif
+diff --git a/drivers/mtd/nand/bmt.h b/drivers/mtd/nand/bmt.h
+new file mode 100644
+index 0000000..2d30ea9
+--- /dev/null
++++ b/drivers/mtd/nand/bmt.h
+@@ -0,0 +1,80 @@
++#ifndef __BMT_H__
++#define __BMT_H__
++
++#include "nand_def.h"
++
++#if defined(__PRELOADER_NAND__)
++
++#include "nand.h"
++
++#elif defined(__UBOOT_NAND__)
++
++#include <linux/mtd/nand.h>
++#include "mtk_nand.h"
++
++#elif defined(__KERNEL_NAND__)
++
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/nand.h>
++#include <linux/module.h>
++#include "mtk_nand.h"
++
++#endif
++
++
++#define MAX_BMT_SIZE        (0x80)
++#define BMT_VERSION         (1) // initial version
++
++#define MAIN_SIGNATURE_OFFSET   (0)
++#define OOB_SIGNATURE_OFFSET    (1)
++#define OOB_INDEX_OFFSET        (29)
++#define OOB_INDEX_SIZE          (2)
++#define FAKE_INDEX              (0xAAAA)
++
++typedef struct _bmt_entry_
++{
++    u16 bad_index;              // bad block index
++    u16 mapped_index;           // mapping block index in the replace pool
++} bmt_entry;
++
++typedef enum
++{
++    UPDATE_ERASE_FAIL,
++    UPDATE_WRITE_FAIL,
++    UPDATE_UNMAPPED_BLOCK,
++    UPDATE_REASON_COUNT,
++} update_reason_t;
++
++typedef struct
++{
++    bmt_entry table[MAX_BMT_SIZE];
++    u8 version;
++    u8 mapped_count;            // mapped block count in pool
++    u8 bad_count;               // bad block count in pool. Not used in V1
++} bmt_struct;
++
++/***************************************************************
++*                                                              *
++* Interface BMT need to use                                    *
++*                                                              *
++***************************************************************/
++extern bool mtk_nand_exec_read_page(struct mtd_info *mtd, u32 row, u32 page_size, u8 * dat, u8 * oob);
++extern int mtk_nand_block_bad_hw(struct mtd_info *mtd, loff_t ofs);
++extern int mtk_nand_erase_hw(struct mtd_info *mtd, int page);
++extern int mtk_nand_block_markbad_hw(struct mtd_info *mtd, loff_t ofs);
++extern int mtk_nand_exec_write_page(struct mtd_info *mtd, u32 row, u32 page_size, u8 * dat, u8 * oob);
++
++
++/***************************************************************
++*                                                              *
++* Different function interface for preloader/uboot/kernel      *
++*                                                              *
++***************************************************************/
++void set_bad_index_to_oob(u8 * oob, u16 index);
++
++
++bmt_struct *init_bmt(struct nand_chip *nand, int size);
++bool update_bmt(u32 offset, update_reason_t reason, u8 * dat, u8 * oob);
++unsigned short get_mapping_block_index(int index);
++
++#endif                          // #ifndef __BMT_H__
+diff --git a/drivers/mtd/nand/dev-nand.c b/drivers/mtd/nand/dev-nand.c
+new file mode 100644
+index 0000000..9fb5235
+--- /dev/null
++++ b/drivers/mtd/nand/dev-nand.c
+@@ -0,0 +1,63 @@
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++
++#include "mt6575_typedefs.h"
++
++#define RALINK_NAND_CTRL_BASE               0xBE003000
++#define NFI_base    RALINK_NAND_CTRL_BASE
++#define RALINK_NANDECC_CTRL_BASE    0xBE003800
++#define NFIECC_base RALINK_NANDECC_CTRL_BASE
++#define MT7621_NFI_IRQ_ID		SURFBOARDINT_NAND
++#define MT7621_NFIECC_IRQ_ID	SURFBOARDINT_NAND_ECC
++
++#define SURFBOARDINT_NAND 22
++#define SURFBOARDINT_NAND_ECC 23
++
++static struct resource MT7621_resource_nand[] = {
++        {
++                .start          = NFI_base,
++                .end            = NFI_base + 0x1A0,
++                .flags          = IORESOURCE_MEM,
++        },
++        {
++                .start          = NFIECC_base,
++                .end            = NFIECC_base + 0x150,
++                .flags          = IORESOURCE_MEM,
++        },
++        {
++                .start          = MT7621_NFI_IRQ_ID,
++                .flags          = IORESOURCE_IRQ,
++        },
++        {
++                .start          = MT7621_NFIECC_IRQ_ID,
++                .flags          = IORESOURCE_IRQ,
++        },
++};
++
++static struct platform_device MT7621_nand_dev = {
++    .name = "MT7621-NAND",
++    .id   = 0,
++        .num_resources  = ARRAY_SIZE(MT7621_resource_nand),
++        .resource               = MT7621_resource_nand,
++    .dev            = {
++        .platform_data = &mt7621_nand_hw,
++    },
++};
++
++
++int __init mtk_nand_register(void)
++{
++
++	int retval = 0;
++
++	retval = platform_device_register(&MT7621_nand_dev);
++	if (retval != 0) {
++		printk(KERN_ERR "register nand device fail\n");
++		return retval;
++	}
++
++
++	return retval;
++}
++arch_initcall(mtk_nand_register);
+diff --git a/drivers/mtd/nand/mt6575_typedefs.h b/drivers/mtd/nand/mt6575_typedefs.h
+new file mode 100644
+index 0000000..a7b9647
+--- /dev/null
++++ b/drivers/mtd/nand/mt6575_typedefs.h
+@@ -0,0 +1,340 @@
++/* Copyright Statement:
++ *
++ * This software/firmware and related documentation ("MediaTek Software") are
++ * protected under relevant copyright laws. The information contained herein
++ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
++ * Without the prior written permission of MediaTek inc. and/or its licensors,
++ * any reproduction, modification, use or disclosure of MediaTek Software,
++ * and information contained herein, in whole or in part, shall be strictly prohibited.
++ */
++/* MediaTek Inc. (C) 2010. All rights reserved.
++ *
++ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
++ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
++ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
++ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
++ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
++ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
++ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
++ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
++ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++ *
++ * The following software/firmware and/or related documentation ("MediaTek Software")
++ * have been modified by MediaTek Inc. All revisions are subject to any receiver's
++ * applicable license agreements with MediaTek Inc.
++ */
++
++/*****************************************************************************
++*  Copyright Statement:
++*  --------------------
++*  This software is protected by Copyright and the information contained
++*  herein is confidential. The software may not be copied and the information
++*  contained herein may not be used or disclosed except with the written
++*  permission of MediaTek Inc. (C) 2008
++*
++*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
++*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
++*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
++*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
++*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
++*
++*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
++*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
++*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++*
++*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
++*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
++*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
++*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
++*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
++*
++*****************************************************************************/
++
++#ifndef _MT6575_TYPEDEFS_H
++#define _MT6575_TYPEDEFS_H
++
++#if defined (__KERNEL_NAND__)
++#include <linux/bug.h>
++#else
++#define true 		1 
++#define false 		0  
++#define bool		u8
++#endif
++
++// ---------------------------------------------------------------------------
++//  Basic Type Definitions
++// ---------------------------------------------------------------------------
++
++typedef volatile unsigned char  *P_kal_uint8;
++typedef volatile unsigned short *P_kal_uint16;
++typedef volatile unsigned int   *P_kal_uint32;
++
++typedef long            LONG;
++typedef unsigned char   UBYTE;
++typedef short           SHORT;
++
++typedef signed char     kal_int8;
++typedef signed short    kal_int16;
++typedef signed int      kal_int32;
++typedef long long       kal_int64;
++typedef unsigned char   kal_uint8;
++typedef unsigned short  kal_uint16;
++typedef unsigned int    kal_uint32;
++typedef unsigned long long  kal_uint64;
++typedef char            kal_char;
++
++typedef unsigned int            *UINT32P;
++typedef volatile unsigned short *UINT16P;
++typedef volatile unsigned char  *UINT8P;
++typedef unsigned char           *U8P;
++
++typedef volatile unsigned char  *P_U8;
++typedef volatile signed char    *P_S8;
++typedef volatile unsigned short *P_U16;
++typedef volatile signed short   *P_S16;
++typedef volatile unsigned int   *P_U32;
++typedef volatile signed int     *P_S32;
++typedef unsigned long long      *P_U64;
++typedef signed long long        *P_S64;
++
++typedef unsigned char       U8;
++typedef signed char         S8;
++typedef unsigned short      U16;
++typedef signed short        S16;
++typedef unsigned int        U32;
++typedef signed int          S32;
++typedef unsigned long long  U64;
++typedef signed long long    S64;
++//typedef unsigned char       bool;
++
++typedef unsigned char   UINT8;
++typedef unsigned short  UINT16;
++typedef unsigned int    UINT32;
++typedef unsigned short  USHORT;
++typedef signed char     INT8;
++typedef signed short    INT16;
++typedef signed int      INT32;
++typedef unsigned int    DWORD;
++typedef void            VOID;
++typedef unsigned char   BYTE;
++typedef float           FLOAT;
++
++typedef char           *LPCSTR;
++typedef short          *LPWSTR;
++
++
++// ---------------------------------------------------------------------------
++//  Constants
++// ---------------------------------------------------------------------------
++
++#define IMPORT  EXTERN
++#ifndef __cplusplus
++  #define EXTERN  extern
++#else
++  #define EXTERN  extern "C"
++#endif
++#define LOCAL     static
++#define GLOBAL
++#define EXPORT    GLOBAL
++
++#define EQ        ==
++#define NEQ       !=
++#define AND       &&
++#define OR        ||
++#define XOR(A,B)  ((!(A) AND (B)) OR ((A) AND !(B)))
++
++#ifndef FALSE
++  #define FALSE (0)
++#endif
++
++#ifndef TRUE
++  #define TRUE  (1)
++#endif
++
++#ifndef NULL
++  #define NULL  (0)
++#endif
++
++//enum boolean {false, true};
++enum {RX, TX, NONE};
++
++#ifndef BOOL
++typedef unsigned char  BOOL;
++#endif
++
++typedef enum {
++   KAL_FALSE = 0,
++   KAL_TRUE  = 1,
++} kal_bool;
++
++
++// ---------------------------------------------------------------------------
++//  Type Casting
++// ---------------------------------------------------------------------------
++
++#define AS_INT32(x)     (*(INT32 *)((void*)x))
++#define AS_INT16(x)     (*(INT16 *)((void*)x))
++#define AS_INT8(x)      (*(INT8  *)((void*)x))
++
++#define AS_UINT32(x)    (*(UINT32 *)((void*)x))
++#define AS_UINT16(x)    (*(UINT16 *)((void*)x))
++#define AS_UINT8(x)     (*(UINT8  *)((void*)x))
++
++
++// ---------------------------------------------------------------------------
++//  Register Manipulations
++// ---------------------------------------------------------------------------
++
++#define READ_REGISTER_UINT32(reg) \
++    (*(volatile UINT32 * const)(reg))
++
++#define WRITE_REGISTER_UINT32(reg, val) \
++    (*(volatile UINT32 * const)(reg)) = (val)
++
++#define READ_REGISTER_UINT16(reg) \
++    (*(volatile UINT16 * const)(reg))
++
++#define WRITE_REGISTER_UINT16(reg, val) \
++    (*(volatile UINT16 * const)(reg)) = (val)
++
++#define READ_REGISTER_UINT8(reg) \
++    (*(volatile UINT8 * const)(reg))
++
++#define WRITE_REGISTER_UINT8(reg, val) \
++    (*(volatile UINT8 * const)(reg)) = (val)
++
++#define INREG8(x)           READ_REGISTER_UINT8((UINT8*)((void*)(x)))
++#define OUTREG8(x, y)       WRITE_REGISTER_UINT8((UINT8*)((void*)(x)), (UINT8)(y))
++#define SETREG8(x, y)       OUTREG8(x, INREG8(x)|(y))
++#define CLRREG8(x, y)       OUTREG8(x, INREG8(x)&~(y))
++#define MASKREG8(x, y, z)   OUTREG8(x, (INREG8(x)&~(y))|(z))
++
++#define INREG16(x)          READ_REGISTER_UINT16((UINT16*)((void*)(x)))
++#define OUTREG16(x, y)      WRITE_REGISTER_UINT16((UINT16*)((void*)(x)),(UINT16)(y))
++#define SETREG16(x, y)      OUTREG16(x, INREG16(x)|(y))
++#define CLRREG16(x, y)      OUTREG16(x, INREG16(x)&~(y))
++#define MASKREG16(x, y, z)  OUTREG16(x, (INREG16(x)&~(y))|(z))
++
++#define INREG32(x)          READ_REGISTER_UINT32((UINT32*)((void*)(x)))
++#define OUTREG32(x, y)      WRITE_REGISTER_UINT32((UINT32*)((void*)(x)), (UINT32)(y))
++#define SETREG32(x, y)      OUTREG32(x, INREG32(x)|(y))
++#define CLRREG32(x, y)      OUTREG32(x, INREG32(x)&~(y))
++#define MASKREG32(x, y, z)  OUTREG32(x, (INREG32(x)&~(y))|(z))
++
++
++#define DRV_Reg8(addr)              INREG8(addr)
++#define DRV_WriteReg8(addr, data)   OUTREG8(addr, data)
++#define DRV_SetReg8(addr, data)     SETREG8(addr, data)
++#define DRV_ClrReg8(addr, data)     CLRREG8(addr, data)
++
++#define DRV_Reg16(addr)             INREG16(addr)
++#define DRV_WriteReg16(addr, data)  OUTREG16(addr, data)
++#define DRV_SetReg16(addr, data)    SETREG16(addr, data)
++#define DRV_ClrReg16(addr, data)    CLRREG16(addr, data)
++
++#define DRV_Reg32(addr)             INREG32(addr)
++#define DRV_WriteReg32(addr, data)  OUTREG32(addr, data)
++#define DRV_SetReg32(addr, data)    SETREG32(addr, data)
++#define DRV_ClrReg32(addr, data)    CLRREG32(addr, data)
++
++// !!! DEPRECATED, WILL BE REMOVED LATER !!!
++#define DRV_Reg(addr)               DRV_Reg16(addr)
++#define DRV_WriteReg(addr, data)    DRV_WriteReg16(addr, data)
++#define DRV_SetReg(addr, data)      DRV_SetReg16(addr, data)
++#define DRV_ClrReg(addr, data)      DRV_ClrReg16(addr, data)
++
++
++// ---------------------------------------------------------------------------
++//  Compiler Time Deduction Macros
++// ---------------------------------------------------------------------------
++
++#define _MASK_OFFSET_1(x, n)  ((x) & 0x1) ? (n) :
++#define _MASK_OFFSET_2(x, n)  _MASK_OFFSET_1((x), (n)) _MASK_OFFSET_1((x) >> 1, (n) + 1)
++#define _MASK_OFFSET_4(x, n)  _MASK_OFFSET_2((x), (n)) _MASK_OFFSET_2((x) >> 2, (n) + 2)
++#define _MASK_OFFSET_8(x, n)  _MASK_OFFSET_4((x), (n)) _MASK_OFFSET_4((x) >> 4, (n) + 4)
++#define _MASK_OFFSET_16(x, n) _MASK_OFFSET_8((x), (n)) _MASK_OFFSET_8((x) >> 8, (n) + 8)
++#define _MASK_OFFSET_32(x, n) _MASK_OFFSET_16((x), (n)) _MASK_OFFSET_16((x) >> 16, (n) + 16)
++
++#define MASK_OFFSET_ERROR (0xFFFFFFFF)
++
++#define MASK_OFFSET(x) (_MASK_OFFSET_32(x, 0) MASK_OFFSET_ERROR)
++
++
++// ---------------------------------------------------------------------------
++//  Assertions
++// ---------------------------------------------------------------------------
++
++#ifndef ASSERT
++    #define ASSERT(expr)        BUG_ON(!(expr))
++#endif
++
++#ifndef NOT_IMPLEMENTED
++    #define NOT_IMPLEMENTED()   BUG_ON(1)
++#endif    
++
++#define STATIC_ASSERT(pred)         STATIC_ASSERT_X(pred, __LINE__)
++#define STATIC_ASSERT_X(pred, line) STATIC_ASSERT_XX(pred, line)
++#define STATIC_ASSERT_XX(pred, line) \
++    extern char assertion_failed_at_##line[(pred) ? 1 : -1]
++
++// ---------------------------------------------------------------------------
++//  Resolve Compiler Warnings
++// ---------------------------------------------------------------------------
++
++#define NOT_REFERENCED(x)   { (x) = (x); }
++
++
++// ---------------------------------------------------------------------------
++//  Utilities
++// ---------------------------------------------------------------------------
++
++#define MAXIMUM(A,B)       (((A)>(B))?(A):(B))
++#define MINIMUM(A,B)       (((A)<(B))?(A):(B))
++
++#define ARY_SIZE(x) (sizeof((x)) / sizeof((x[0])))
++#define DVT_DELAYMACRO(u4Num)                                            \
++{                                                                        \
++    UINT32 u4Count = 0 ;                                                 \
++    for (u4Count = 0; u4Count < u4Num; u4Count++ );                      \
++}                                                                        \
++
++#define    A68351B      0
++#define    B68351B      1
++#define    B68351D      2
++#define    B68351E      3
++#define    UNKNOWN_IC_VERSION   0xFF
++
++/* NAND driver */
++struct mtk_nand_host_hw {
++    unsigned int nfi_bus_width;		    /* NFI_BUS_WIDTH */ 
++	unsigned int nfi_access_timing;		/* NFI_ACCESS_TIMING */  
++	unsigned int nfi_cs_num;			/* NFI_CS_NUM */
++	unsigned int nand_sec_size;			/* NAND_SECTOR_SIZE */
++	unsigned int nand_sec_shift;		/* NAND_SECTOR_SHIFT */
++	unsigned int nand_ecc_size;
++	unsigned int nand_ecc_bytes;
++	unsigned int nand_ecc_mode;
++};
++extern struct mtk_nand_host_hw mt7621_nand_hw;
++extern unsigned int	CFG_BLOCKSIZE;
++
++#endif  // _MT6575_TYPEDEFS_H
++
+diff --git a/drivers/mtd/nand/mtk_nand.c b/drivers/mtd/nand/mtk_nand.c
+new file mode 100644
+index 0000000..00e150c
+--- /dev/null
++++ b/drivers/mtd/nand/mtk_nand.c
+@@ -0,0 +1,2304 @@
++/******************************************************************************
++* mtk_nand.c - MTK NAND Flash Device Driver
++ *
++* Copyright 2009-2012 MediaTek Co.,Ltd.
++ *
++* DESCRIPTION:
++* 	This file provid the other drivers nand relative functions
++ *
++* modification history
++* ----------------------------------------
++* v3.0, 11 Feb 2010, mtk
++* ----------------------------------------
++******************************************************************************/
++#include "nand_def.h"
++#include <linux/slab.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++#include <linux/sched.h>
++#include <linux/types.h>
++#include <linux/wait.h>
++#include <linux/spinlock.h>
++#include <linux/interrupt.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/nand.h>
++#include <linux/mtd/partitions.h>
++#include <linux/mtd/nand_ecc.h>
++#include <linux/dma-mapping.h>
++#include <linux/jiffies.h>
++#include <linux/platform_device.h>
++#include <linux/proc_fs.h>
++#include <linux/time.h>
++#include <linux/mm.h>
++#include <asm/io.h>
++#include <asm/cacheflush.h>
++#include <asm/uaccess.h>
++#include <linux/miscdevice.h>
++#include "mtk_nand.h"
++#include "nand_device_list.h"
++
++#include "bmt.h"
++#include "partition.h"
++
++unsigned int CFG_BLOCKSIZE;
++
++static int shift_on_bbt = 0;
++extern void nand_bbt_set(struct mtd_info *mtd, int page, int flag);
++extern int nand_bbt_get(struct mtd_info *mtd, int page);
++int mtk_nand_read_oob_hw(struct mtd_info *mtd, struct nand_chip *chip, int page);
++
++static const char * const probe_types[] = { "cmdlinepart", "ofpart", NULL };
++
++#define NAND_CMD_STATUS_MULTI  0x71
++
++void show_stack(struct task_struct *tsk, unsigned long *sp);
++extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
++extern void mt_irq_set_polarity(unsigned int irq,unsigned int polarity);
++
++struct mtk_nand_host	mtk_nand_host;	/* include mtd_info and nand_chip structs */
++struct mtk_nand_host_hw mt7621_nand_hw = {
++    .nfi_bus_width          = 8,
++    .nfi_access_timing      = NFI_DEFAULT_ACCESS_TIMING,
++    .nfi_cs_num             = NFI_CS_NUM,
++    .nand_sec_size          = 512,
++    .nand_sec_shift         = 9,
++    .nand_ecc_size          = 2048,
++    .nand_ecc_bytes         = 32,
++    .nand_ecc_mode          = NAND_ECC_HW,
++};
++
++
++/*******************************************************************************
++ * Gloable Varible Definition
++ *******************************************************************************/
++
++#define NFI_ISSUE_COMMAND(cmd, col_addr, row_addr, col_num, row_num) \
++   do { \
++      DRV_WriteReg(NFI_CMD_REG16,cmd);\
++      while (DRV_Reg32(NFI_STA_REG32) & STA_CMD_STATE);\
++      DRV_WriteReg32(NFI_COLADDR_REG32, col_addr);\
++      DRV_WriteReg32(NFI_ROWADDR_REG32, row_addr);\
++      DRV_WriteReg(NFI_ADDRNOB_REG16, col_num | (row_num<<ADDR_ROW_NOB_SHIFT));\
++      while (DRV_Reg32(NFI_STA_REG32) & STA_ADDR_STATE);\
++   }while(0);
++
++//-------------------------------------------------------------------------------
++static struct NAND_CMD g_kCMD;
++static u32 g_u4ChipVer;
++bool g_bInitDone;
++static bool g_bcmdstatus;
++static u32 g_value = 0;
++static int g_page_size;
++
++BOOL g_bHwEcc = true;
++
++
++static u8 *local_buffer_16_align;   // 16 byte aligned buffer, for HW issue
++static u8 local_buffer[4096 + 512];
++
++extern void nand_release_device(struct mtd_info *mtd);
++extern int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state);
++
++#if defined(MTK_NAND_BMT)
++static bmt_struct *g_bmt;
++#endif
++struct mtk_nand_host *host;
++extern struct mtd_partition g_pasStatic_Partition[];
++int part_num = NUM_PARTITIONS;
++int manu_id;
++int dev_id;
++
++static u8 local_oob_buf[NAND_MAX_OOBSIZE];
++
++static u8 nand_badblock_offset = 0;
++
++void nand_enable_clock(void)
++{
++    //enable_clock(MT65XX_PDN_PERI_NFI, "NAND");
++}
++
++void nand_disable_clock(void)
++{
++    //disable_clock(MT65XX_PDN_PERI_NFI, "NAND");
++}
++
++static struct nand_ecclayout nand_oob_16 = {
++	.eccbytes = 8,
++	.eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
++	.oobfree = {{1, 6}, {0, 0}}
++};
++
++struct nand_ecclayout nand_oob_64 = {
++	.eccbytes = 32,
++	.eccpos = {32, 33, 34, 35, 36, 37, 38, 39,
++		40, 41, 42, 43, 44, 45, 46, 47,
++		48, 49, 50, 51, 52, 53, 54, 55,
++		56, 57, 58, 59, 60, 61, 62, 63},
++	.oobfree = {{1, 7}, {9, 7}, {17, 7}, {25, 6}, {0, 0}}
++};
++
++struct nand_ecclayout nand_oob_128 = {
++	.eccbytes = 64,
++	.eccpos = {
++		64, 65, 66, 67, 68, 69, 70, 71,
++		72, 73, 74, 75, 76, 77, 78, 79,
++		80, 81, 82, 83, 84, 85, 86, 86,
++		88, 89, 90, 91, 92, 93, 94, 95,
++		96, 97, 98, 99, 100, 101, 102, 103,
++		104, 105, 106, 107, 108, 109, 110, 111,
++		112, 113, 114, 115, 116, 117, 118, 119,
++		120, 121, 122, 123, 124, 125, 126, 127},
++	.oobfree = {{1, 7}, {9, 7}, {17, 7}, {25, 7}, {33, 7}, {41, 7}, {49, 7}, {57, 6}}
++};
++
++flashdev_info devinfo;
++
++void dump_nfi(void)
++{
++}
++
++void dump_ecc(void)
++{
++}
++
++u32
++nand_virt_to_phys_add(u32 va)
++{
++	u32 pageOffset = (va & (PAGE_SIZE - 1));
++	pgd_t *pgd;
++	pmd_t *pmd;
++	pte_t *pte;
++	u32 pa;
++
++	if (virt_addr_valid(va))
++		return __virt_to_phys(va);
++
++	if (NULL == current) {
++		printk(KERN_ERR "[nand_virt_to_phys_add] ERROR ,current is NULL! \n");
++		return 0;
++	}
++
++	if (NULL == current->mm) {
++		printk(KERN_ERR "[nand_virt_to_phys_add] ERROR current->mm is NULL! tgid=0x%x, name=%s \n", current->tgid, current->comm);
++		return 0;
++	}
++
++	pgd = pgd_offset(current->mm, va);  /* what is tsk->mm */
++	if (pgd_none(*pgd) || pgd_bad(*pgd)) {
++		printk(KERN_ERR "[nand_virt_to_phys_add] ERROR, va=0x%x, pgd invalid! \n", va);
++		return 0;
++	}
++
++	pmd = pmd_offset((pud_t *)pgd, va);
++	if (pmd_none(*pmd) || pmd_bad(*pmd)) {
++		printk(KERN_ERR "[nand_virt_to_phys_add] ERROR, va=0x%x, pmd invalid! \n", va);
++		return 0;
++	}
++
++	pte = pte_offset_map(pmd, va);
++	if (pte_present(*pte)) {
++		pa = (pte_val(*pte) & (PAGE_MASK)) | pageOffset;
++		return pa;
++	}
++
++	printk(KERN_ERR "[nand_virt_to_phys_add] ERROR va=0x%x, pte invalid! \n", va);
++	return 0;
++}
++EXPORT_SYMBOL(nand_virt_to_phys_add);
++
++bool
++get_device_info(u16 id, u32 ext_id, flashdev_info * pdevinfo)
++{
++	u32 index;
++	for (index = 0; gen_FlashTable[index].id != 0; index++) {
++		if (id == gen_FlashTable[index].id && ext_id == gen_FlashTable[index].ext_id) {
++			pdevinfo->id = gen_FlashTable[index].id;
++			pdevinfo->ext_id = gen_FlashTable[index].ext_id;
++			pdevinfo->blocksize = gen_FlashTable[index].blocksize;
++			pdevinfo->addr_cycle = gen_FlashTable[index].addr_cycle;
++			pdevinfo->iowidth = gen_FlashTable[index].iowidth;
++			pdevinfo->timmingsetting = gen_FlashTable[index].timmingsetting;
++			pdevinfo->advancedmode = gen_FlashTable[index].advancedmode;
++			pdevinfo->pagesize = gen_FlashTable[index].pagesize;
++			pdevinfo->sparesize = gen_FlashTable[index].sparesize;
++			pdevinfo->totalsize = gen_FlashTable[index].totalsize;
++			memcpy(pdevinfo->devciename, gen_FlashTable[index].devciename, sizeof(pdevinfo->devciename));
++			printk(KERN_INFO "Device found in MTK table, ID: %x, EXT_ID: %x\n", id, ext_id);
++
++			goto find;
++		}
++	}
++
++find:
++	if (0 == pdevinfo->id) {
++		printk(KERN_INFO "Device not found, ID: %x\n", id);
++		return false;
++	} else {
++		return true;
++	}
++}
++
++static void
++ECC_Config(struct mtk_nand_host_hw *hw,u32 ecc_bit)
++{
++	u32 u4ENCODESize;
++	u32 u4DECODESize;
++	u32 ecc_bit_cfg = ECC_CNFG_ECC4;
++
++	switch(ecc_bit){
++	case 4:
++		ecc_bit_cfg = ECC_CNFG_ECC4;
++		break;
++	case 8:
++		ecc_bit_cfg = ECC_CNFG_ECC8;
++		break;
++	case 10:
++		ecc_bit_cfg = ECC_CNFG_ECC10;
++		break;
++	case 12:
++		ecc_bit_cfg = ECC_CNFG_ECC12;
++		break;
++	default:
++		break;
++	}
++	DRV_WriteReg16(ECC_DECCON_REG16, DEC_DE);
++	do {
++	} while (!DRV_Reg16(ECC_DECIDLE_REG16));
++
++	DRV_WriteReg16(ECC_ENCCON_REG16, ENC_DE);
++	do {
++	} while (!DRV_Reg32(ECC_ENCIDLE_REG32));
++
++	/* setup FDM register base */
++	DRV_WriteReg32(ECC_FDMADDR_REG32, NFI_FDM0L_REG32);
++
++	/* Sector + FDM */
++	u4ENCODESize = (hw->nand_sec_size + 8) << 3;
++	/* Sector + FDM + YAFFS2 meta data bits */
++	u4DECODESize = ((hw->nand_sec_size + 8) << 3) + ecc_bit * 13;
++
++	/* configure ECC decoder && encoder */
++	DRV_WriteReg32(ECC_DECCNFG_REG32, ecc_bit_cfg | DEC_CNFG_NFI | DEC_CNFG_EMPTY_EN | (u4DECODESize << DEC_CNFG_CODE_SHIFT));
++
++	DRV_WriteReg32(ECC_ENCCNFG_REG32, ecc_bit_cfg | ENC_CNFG_NFI | (u4ENCODESize << ENC_CNFG_MSG_SHIFT));
++	NFI_SET_REG32(ECC_DECCNFG_REG32, DEC_CNFG_EL);
++}
++
++static void
++ECC_Decode_Start(void)
++{
++	while (!(DRV_Reg16(ECC_DECIDLE_REG16) & DEC_IDLE))
++		;
++	DRV_WriteReg16(ECC_DECCON_REG16, DEC_EN);
++}
++
++static void
++ECC_Decode_End(void)
++{
++	while (!(DRV_Reg16(ECC_DECIDLE_REG16) & DEC_IDLE))
++		;
++	DRV_WriteReg16(ECC_DECCON_REG16, DEC_DE);
++}
++
++static void
++ECC_Encode_Start(void)
++{
++	while (!(DRV_Reg32(ECC_ENCIDLE_REG32) & ENC_IDLE))
++		;
++	mb();
++	DRV_WriteReg16(ECC_ENCCON_REG16, ENC_EN);
++}
++
++static void
++ECC_Encode_End(void)
++{
++	/* wait for device returning idle */
++	while (!(DRV_Reg32(ECC_ENCIDLE_REG32) & ENC_IDLE)) ;
++	mb();
++	DRV_WriteReg16(ECC_ENCCON_REG16, ENC_DE);
++}
++
++static bool
++mtk_nand_check_bch_error(struct mtd_info *mtd, u8 * pDataBuf, u32 u4SecIndex, u32 u4PageAddr)
++{
++	bool bRet = true;
++	u16 u2SectorDoneMask = 1 << u4SecIndex;
++	u32 u4ErrorNumDebug, i, u4ErrNum;
++	u32 timeout = 0xFFFF;
++	// int el;
++	u32 au4ErrBitLoc[6];
++	u32 u4ErrByteLoc, u4BitOffset;
++	u32 u4ErrBitLoc1th, u4ErrBitLoc2nd;
++
++	//4 // Wait for Decode Done
++	while (0 == (u2SectorDoneMask & DRV_Reg16(ECC_DECDONE_REG16))) {
++		timeout--;
++		if (0 == timeout)
++			return false;
++	}
++	/* We will manually correct the error bits in the last sector, not all the sectors of the page! */
++	memset(au4ErrBitLoc, 0x0, sizeof(au4ErrBitLoc));
++	u4ErrorNumDebug = DRV_Reg32(ECC_DECENUM_REG32);
++	u4ErrNum = DRV_Reg32(ECC_DECENUM_REG32) >> (u4SecIndex << 2);
++	u4ErrNum &= 0xF;
++
++	if (u4ErrNum) {
++		if (0xF == u4ErrNum) {
++			mtd->ecc_stats.failed++;
++			bRet = false;
++			//printk(KERN_ERR"UnCorrectable at PageAddr=%d\n", u4PageAddr);
++		} else {
++			for (i = 0; i < ((u4ErrNum + 1) >> 1); ++i) {
++				au4ErrBitLoc[i] = DRV_Reg32(ECC_DECEL0_REG32 + i);
++				u4ErrBitLoc1th = au4ErrBitLoc[i] & 0x1FFF;
++				if (u4ErrBitLoc1th < 0x1000) {
++					u4ErrByteLoc = u4ErrBitLoc1th / 8;
++					u4BitOffset = u4ErrBitLoc1th % 8;
++					pDataBuf[u4ErrByteLoc] = pDataBuf[u4ErrByteLoc] ^ (1 << u4BitOffset);
++					mtd->ecc_stats.corrected++;
++				} else {
++					mtd->ecc_stats.failed++;
++				}
++				u4ErrBitLoc2nd = (au4ErrBitLoc[i] >> 16) & 0x1FFF;
++				if (0 != u4ErrBitLoc2nd) {
++					if (u4ErrBitLoc2nd < 0x1000) {
++						u4ErrByteLoc = u4ErrBitLoc2nd / 8;
++						u4BitOffset = u4ErrBitLoc2nd % 8;
++						pDataBuf[u4ErrByteLoc] = pDataBuf[u4ErrByteLoc] ^ (1 << u4BitOffset);
++						mtd->ecc_stats.corrected++;
++					} else {
++						mtd->ecc_stats.failed++;
++						//printk(KERN_ERR"UnCorrectable High ErrLoc=%d\n", au4ErrBitLoc[i]);
++					}
++				}
++			}
++		}
++		if (0 == (DRV_Reg16(ECC_DECFER_REG16) & (1 << u4SecIndex)))
++			bRet = false;
++	}
++	return bRet;
++}
++
++static bool
++mtk_nand_RFIFOValidSize(u16 u2Size)
++{
++	u32 timeout = 0xFFFF;
++	while (FIFO_RD_REMAIN(DRV_Reg16(NFI_FIFOSTA_REG16)) < u2Size) {
++		timeout--;
++		if (0 == timeout)
++			return false;
++	}
++	return true;
++}
++
++static bool
++mtk_nand_WFIFOValidSize(u16 u2Size)
++{
++	u32 timeout = 0xFFFF;
++
++	while (FIFO_WR_REMAIN(DRV_Reg16(NFI_FIFOSTA_REG16)) > u2Size) {
++		timeout--;
++		if (0 == timeout)
++			return false;
++	}
++	return true;
++}
++
++static bool
++mtk_nand_status_ready(u32 u4Status)
++{
++	u32 timeout = 0xFFFF;
++
++	while ((DRV_Reg32(NFI_STA_REG32) & u4Status) != 0) {
++		timeout--;
++		if (0 == timeout)
++			return false;
++	}
++	return true;
++}
++
++static bool
++mtk_nand_reset(void)
++{
++	int timeout = 0xFFFF;
++	if (DRV_Reg16(NFI_MASTERSTA_REG16)) {
++		mb();
++		DRV_WriteReg16(NFI_CON_REG16, CON_FIFO_FLUSH | CON_NFI_RST);
++		while (DRV_Reg16(NFI_MASTERSTA_REG16)) {
++			timeout--;
++			if (!timeout)
++				MSG(INIT, "Wait for NFI_MASTERSTA timeout\n");
++		}
++	}
++	/* issue reset operation */
++	mb();
++	DRV_WriteReg16(NFI_CON_REG16, CON_FIFO_FLUSH | CON_NFI_RST);
++
++	return mtk_nand_status_ready(STA_NFI_FSM_MASK | STA_NAND_BUSY) && mtk_nand_RFIFOValidSize(0) && mtk_nand_WFIFOValidSize(0);
++}
++
++static void
++mtk_nand_set_mode(u16 u2OpMode)
++{
++	u16 u2Mode = DRV_Reg16(NFI_CNFG_REG16);
++	u2Mode &= ~CNFG_OP_MODE_MASK;
++	u2Mode |= u2OpMode;
++	DRV_WriteReg16(NFI_CNFG_REG16, u2Mode);
++}
++
++static void
++mtk_nand_set_autoformat(bool bEnable)
++{
++	if (bEnable)
++		NFI_SET_REG16(NFI_CNFG_REG16, CNFG_AUTO_FMT_EN);
++	else
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AUTO_FMT_EN);
++}
++
++static void
++mtk_nand_configure_fdm(u16 u2FDMSize)
++{
++	NFI_CLN_REG16(NFI_PAGEFMT_REG16, PAGEFMT_FDM_MASK | PAGEFMT_FDM_ECC_MASK);
++	NFI_SET_REG16(NFI_PAGEFMT_REG16, u2FDMSize << PAGEFMT_FDM_SHIFT);
++	NFI_SET_REG16(NFI_PAGEFMT_REG16, u2FDMSize << PAGEFMT_FDM_ECC_SHIFT);
++}
++
++static void
++mtk_nand_configure_lock(void)
++{
++	u32 u4WriteColNOB = 2;
++	u32 u4WriteRowNOB = 3;
++	u32 u4EraseColNOB = 0;
++	u32 u4EraseRowNOB = 3;
++	DRV_WriteReg16(NFI_LOCKANOB_REG16,
++		(u4WriteColNOB << PROG_CADD_NOB_SHIFT) | (u4WriteRowNOB << PROG_RADD_NOB_SHIFT) | (u4EraseColNOB << ERASE_CADD_NOB_SHIFT) | (u4EraseRowNOB << ERASE_RADD_NOB_SHIFT));
++
++	if (CHIPVER_ECO_1 == g_u4ChipVer) {
++		int i;
++		for (i = 0; i < 16; ++i) {
++			DRV_WriteReg32(NFI_LOCK00ADD_REG32 + (i << 1), 0xFFFFFFFF);
++			DRV_WriteReg32(NFI_LOCK00FMT_REG32 + (i << 1), 0xFFFFFFFF);
++		}
++		//DRV_WriteReg16(NFI_LOCKANOB_REG16, 0x0);
++		DRV_WriteReg32(NFI_LOCKCON_REG32, 0xFFFFFFFF);
++		DRV_WriteReg16(NFI_LOCK_REG16, NFI_LOCK_ON);
++	}
++}
++
++static bool
++mtk_nand_pio_ready(void)
++{
++	int count = 0;
++	while (!(DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1)) {
++		count++;
++		if (count > 0xffff) {
++			printk("PIO_DIRDY timeout\n");
++			return false;
++		}
++	}
++
++	return true;
++}
++
++static bool
++mtk_nand_set_command(u16 command)
++{
++	mb();
++	DRV_WriteReg16(NFI_CMD_REG16, command);
++	return mtk_nand_status_ready(STA_CMD_STATE);
++}
++
++static bool
++mtk_nand_set_address(u32 u4ColAddr, u32 u4RowAddr, u16 u2ColNOB, u16 u2RowNOB)
++{
++	mb();
++	DRV_WriteReg32(NFI_COLADDR_REG32, u4ColAddr);
++	DRV_WriteReg32(NFI_ROWADDR_REG32, u4RowAddr);
++	DRV_WriteReg16(NFI_ADDRNOB_REG16, u2ColNOB | (u2RowNOB << ADDR_ROW_NOB_SHIFT));
++	return mtk_nand_status_ready(STA_ADDR_STATE);
++}
++
++static bool
++mtk_nand_check_RW_count(u16 u2WriteSize)
++{
++	u32 timeout = 0xFFFF;
++	u16 u2SecNum = u2WriteSize >> 9;
++
++	while (ADDRCNTR_CNTR(DRV_Reg16(NFI_ADDRCNTR_REG16)) < u2SecNum) {
++		timeout--;
++		if (0 == timeout) {
++			printk(KERN_INFO "[%s] timeout\n", __FUNCTION__);
++			return false;
++		}
++	}
++	return true;
++}
++
++static bool
++mtk_nand_ready_for_read(struct nand_chip *nand, u32 u4RowAddr, u32 u4ColAddr, bool full, u8 * buf)
++{
++	/* Reset NFI HW internal state machine and flush NFI in/out FIFO */
++	bool bRet = false;
++	u16 sec_num = 1 << (nand->page_shift - 9);
++	u32 col_addr = u4ColAddr;
++	u32 colnob = 2, rownob = devinfo.addr_cycle - 2;
++	if (nand->options & NAND_BUSWIDTH_16)
++		col_addr /= 2;
++
++	if (!mtk_nand_reset())
++		goto cleanup;
++	if (g_bHwEcc)	{
++		NFI_SET_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++	} else	{
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++	}
++
++	mtk_nand_set_mode(CNFG_OP_READ);
++	NFI_SET_REG16(NFI_CNFG_REG16, CNFG_READ_EN);
++	DRV_WriteReg16(NFI_CON_REG16, sec_num << CON_NFI_SEC_SHIFT);
++
++	if (full) {
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
++
++		if (g_bHwEcc)
++			NFI_SET_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++		else
++			NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++	} else {
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
++	}
++
++	mtk_nand_set_autoformat(full);
++	if (full)
++		if (g_bHwEcc)
++			ECC_Decode_Start();
++	if (!mtk_nand_set_command(NAND_CMD_READ0))
++		goto cleanup;
++	if (!mtk_nand_set_address(col_addr, u4RowAddr, colnob, rownob))
++		goto cleanup;
++	if (!mtk_nand_set_command(NAND_CMD_READSTART))
++		goto cleanup;
++	if (!mtk_nand_status_ready(STA_NAND_BUSY))
++		goto cleanup;
++
++	bRet = true;
++
++cleanup:
++	return bRet;
++}
++
++static bool
++mtk_nand_ready_for_write(struct nand_chip *nand, u32 u4RowAddr, u32 col_addr, bool full, u8 * buf)
++{
++	bool bRet = false;
++	u32 sec_num = 1 << (nand->page_shift - 9);
++	u32 colnob = 2, rownob = devinfo.addr_cycle - 2;
++	if (nand->options & NAND_BUSWIDTH_16)
++		col_addr /= 2;
++
++	/* Reset NFI HW internal state machine and flush NFI in/out FIFO */
++	if (!mtk_nand_reset())
++		return false;
++
++	mtk_nand_set_mode(CNFG_OP_PRGM);
++
++	NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_READ_EN);
++
++	DRV_WriteReg16(NFI_CON_REG16, sec_num << CON_NFI_SEC_SHIFT);
++
++	if (full) {
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
++		if (g_bHwEcc)
++			NFI_SET_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++		else
++			NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++	} else {
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
++	}
++
++	mtk_nand_set_autoformat(full);
++
++	if (full)
++		if (g_bHwEcc)
++			ECC_Encode_Start();
++
++	if (!mtk_nand_set_command(NAND_CMD_SEQIN))
++		goto cleanup;
++	//1 FIXED ME: For Any Kind of AddrCycle
++	if (!mtk_nand_set_address(col_addr, u4RowAddr, colnob, rownob))
++		goto cleanup;
++
++	if (!mtk_nand_status_ready(STA_NAND_BUSY))
++		goto cleanup;
++
++	bRet = true;
++
++cleanup:
++	return bRet;
++}
++
++static bool
++mtk_nand_check_dececc_done(u32 u4SecNum)
++{
++	u32 timeout, dec_mask;
++
++	timeout = 0xffff;
++	dec_mask = (1 << u4SecNum) - 1;
++	while ((dec_mask != DRV_Reg(ECC_DECDONE_REG16)) && timeout > 0)
++		timeout--;
++	if (timeout == 0) {
++		MSG(VERIFY, "ECC_DECDONE: timeout\n");
++		return false;
++	}
++	return true;
++}
++
++static bool
++mtk_nand_mcu_read_data(u8 * buf, u32 length)
++{
++	int timeout = 0xffff;
++	u32 i;
++	u32 *buf32 = (u32 *) buf;
++	if ((u32) buf % 4 || length % 4)
++		NFI_SET_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
++	else
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
++
++	//DRV_WriteReg32(NFI_STRADDR_REG32, 0);
++	mb();
++	NFI_SET_REG16(NFI_CON_REG16, CON_NFI_BRD);
++
++	if ((u32) buf % 4 || length % 4) {
++		for (i = 0; (i < (length)) && (timeout > 0);) {
++			if (DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1) {
++				*buf++ = (u8) DRV_Reg32(NFI_DATAR_REG32);
++				i++;
++			} else {
++				timeout--;
++			}
++			if (0 == timeout) {
++				printk(KERN_ERR "[%s] timeout\n", __FUNCTION__);
++				dump_nfi();
++				return false;
++			}
++		}
++	} else {
++		for (i = 0; (i < (length >> 2)) && (timeout > 0);) {
++			if (DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1) {
++				*buf32++ = DRV_Reg32(NFI_DATAR_REG32);
++				i++;
++			} else {
++				timeout--;
++			}
++			if (0 == timeout) {
++				printk(KERN_ERR "[%s] timeout\n", __FUNCTION__);
++				dump_nfi();
++				return false;
++			}
++		}
++	}
++	return true;
++}
++
++static bool
++mtk_nand_read_page_data(struct mtd_info *mtd, u8 * pDataBuf, u32 u4Size)
++{
++	return mtk_nand_mcu_read_data(pDataBuf, u4Size);
++}
++
++static bool
++mtk_nand_mcu_write_data(struct mtd_info *mtd, const u8 * buf, u32 length)
++{
++	u32 timeout = 0xFFFF;
++	u32 i;
++	u32 *pBuf32;
++	NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
++	mb();
++	NFI_SET_REG16(NFI_CON_REG16, CON_NFI_BWR);
++	pBuf32 = (u32 *) buf;
++
++	if ((u32) buf % 4 || length % 4)
++		NFI_SET_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
++	else
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
++
++	if ((u32) buf % 4 || length % 4) {
++		for (i = 0; (i < (length)) && (timeout > 0);) {
++			if (DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1) {
++				DRV_WriteReg32(NFI_DATAW_REG32, *buf++);
++				i++;
++			} else {
++				timeout--;
++			}
++			if (0 == timeout) {
++				printk(KERN_ERR "[%s] timeout\n", __FUNCTION__);
++				dump_nfi();
++				return false;
++			}
++		}
++	} else {
++		for (i = 0; (i < (length >> 2)) && (timeout > 0);) {
++			if (DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1) {
++				DRV_WriteReg32(NFI_DATAW_REG32, *pBuf32++);
++				i++;
++			} else {
++				timeout--;
++			}
++			if (0 == timeout) {
++				printk(KERN_ERR "[%s] timeout\n", __FUNCTION__);
++				dump_nfi();
++				return false;
++			}
++		}
++	}
++
++	return true;
++}
++
++static bool
++mtk_nand_write_page_data(struct mtd_info *mtd, u8 * buf, u32 size)
++{
++	return mtk_nand_mcu_write_data(mtd, buf, size);
++}
++
++static void
++mtk_nand_read_fdm_data(u8 * pDataBuf, u32 u4SecNum)
++{
++	u32 i;
++	u32 *pBuf32 = (u32 *) pDataBuf;
++
++	if (pBuf32) {
++		for (i = 0; i < u4SecNum; ++i) {
++			*pBuf32++ = DRV_Reg32(NFI_FDM0L_REG32 + (i << 1));
++			*pBuf32++ = DRV_Reg32(NFI_FDM0M_REG32 + (i << 1));
++		}
++	}
++}
++
++static u8 fdm_buf[64];
++static void
++mtk_nand_write_fdm_data(struct nand_chip *chip, u8 * pDataBuf, u32 u4SecNum)
++{
++	u32 i, j;
++	u8 checksum = 0;
++	bool empty = true;
++	struct nand_oobfree *free_entry;
++	u32 *pBuf32;
++
++	memcpy(fdm_buf, pDataBuf, u4SecNum * 8);
++
++	free_entry = chip->ecc.layout->oobfree;
++	for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free_entry[i].length; i++) {
++		for (j = 0; j < free_entry[i].length; j++) {
++			if (pDataBuf[free_entry[i].offset + j] != 0xFF)
++				empty = false;
++			checksum ^= pDataBuf[free_entry[i].offset + j];
++		}
++	}
++
++	if (!empty) {
++		fdm_buf[free_entry[i - 1].offset + free_entry[i - 1].length] = checksum;
++	}
++
++	pBuf32 = (u32 *) fdm_buf;
++	for (i = 0; i < u4SecNum; ++i) {
++		DRV_WriteReg32(NFI_FDM0L_REG32 + (i << 1), *pBuf32++);
++		DRV_WriteReg32(NFI_FDM0M_REG32 + (i << 1), *pBuf32++);
++	}
++}
++
++static void
++mtk_nand_stop_read(void)
++{
++	NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_BRD);
++	mtk_nand_reset();
++	if (g_bHwEcc)
++		ECC_Decode_End();
++	DRV_WriteReg16(NFI_INTR_EN_REG16, 0);
++}
++
++static void
++mtk_nand_stop_write(void)
++{
++	NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_BWR);
++	if (g_bHwEcc)
++		ECC_Encode_End();
++	DRV_WriteReg16(NFI_INTR_EN_REG16, 0);
++}
++
++bool
++mtk_nand_exec_read_page(struct mtd_info *mtd, u32 u4RowAddr, u32 u4PageSize, u8 * pPageBuf, u8 * pFDMBuf)
++{
++	u8 *buf;
++	bool bRet = true;
++	struct nand_chip *nand = mtd->priv;
++	u32 u4SecNum = u4PageSize >> 9;
++
++	if (((u32) pPageBuf % 16) && local_buffer_16_align)
++		buf = local_buffer_16_align;
++	else
++		buf = pPageBuf;
++	if (mtk_nand_ready_for_read(nand, u4RowAddr, 0, true, buf)) {
++		int j;
++		for (j = 0 ; j < u4SecNum; j++) {
++			if (!mtk_nand_read_page_data(mtd, buf+j*512, 512))
++				bRet = false;
++			if(g_bHwEcc && !mtk_nand_check_dececc_done(j+1))
++				bRet = false;
++			if(g_bHwEcc && !mtk_nand_check_bch_error(mtd, buf+j*512, j, u4RowAddr))
++				bRet = false;
++		}
++		if (!mtk_nand_status_ready(STA_NAND_BUSY))
++			bRet = false;
++
++		mtk_nand_read_fdm_data(pFDMBuf, u4SecNum);
++		mtk_nand_stop_read();
++	}
++
++	if (buf == local_buffer_16_align)
++		memcpy(pPageBuf, buf, u4PageSize);
++
++	return bRet;
++}
++
++int
++mtk_nand_exec_write_page(struct mtd_info *mtd, u32 u4RowAddr, u32 u4PageSize, u8 * pPageBuf, u8 * pFDMBuf)
++{
++	struct nand_chip *chip = mtd->priv;
++	u32 u4SecNum = u4PageSize >> 9;
++	u8 *buf;
++	u8 status;
++
++	MSG(WRITE, "mtk_nand_exec_write_page, page: 0x%x\n", u4RowAddr);
++
++	if (((u32) pPageBuf % 16) && local_buffer_16_align) {
++		printk(KERN_INFO "Data buffer not 16 bytes aligned: %p\n", pPageBuf);
++		memcpy(local_buffer_16_align, pPageBuf, mtd->writesize);
++		buf = local_buffer_16_align;
++	} else
++		buf = pPageBuf;
++
++	if (mtk_nand_ready_for_write(chip, u4RowAddr, 0, true, buf)) {
++		mtk_nand_write_fdm_data(chip, pFDMBuf, u4SecNum);
++		(void)mtk_nand_write_page_data(mtd, buf, u4PageSize);
++		(void)mtk_nand_check_RW_count(u4PageSize);
++		mtk_nand_stop_write();
++		(void)mtk_nand_set_command(NAND_CMD_PAGEPROG);
++		while (DRV_Reg32(NFI_STA_REG32) & STA_NAND_BUSY) ;
++	}
++
++	status = chip->waitfunc(mtd, chip);
++	if (status & NAND_STATUS_FAIL)
++		return -EIO;
++	return 0;
++}
++
++static int
++get_start_end_block(struct mtd_info *mtd, int block, int *start_blk, int *end_blk)
++{
++	struct nand_chip *chip = mtd->priv;
++	int i;
++
++	*start_blk = 0;
++        for (i = 0; i <= part_num; i++)
++        {
++		if (i == part_num)
++		{
++			// try the last reset partition
++			*end_blk = (chip->chipsize >> chip->phys_erase_shift) - 1;
++			if (*start_blk <= *end_blk)
++			{
++				if ((block >= *start_blk) && (block <= *end_blk))
++					break;
++			}
++		}
++		// skip All partition entry
++		else if (g_pasStatic_Partition[i].size == MTDPART_SIZ_FULL)
++		{
++			continue;
++		}
++                *end_blk = *start_blk + (g_pasStatic_Partition[i].size >> chip->phys_erase_shift) - 1;
++                if ((block >= *start_blk) && (block <= *end_blk))
++                        break;
++                *start_blk = *end_blk + 1;
++        }
++        if (*start_blk > *end_blk)
++	{
++                return -1;
++	}
++	return 0;
++}
++
++static int
++block_remap(struct mtd_info *mtd, int block)
++{
++	struct nand_chip *chip = mtd->priv;
++	int start_blk, end_blk;
++	int j, block_offset;
++	int bad_block = 0;
++
++	if (chip->bbt == NULL) {
++		printk("ERROR!! no bbt table for block_remap\n");
++		return -1;
++	}
++
++	if (get_start_end_block(mtd, block, &start_blk, &end_blk) < 0) {
++		printk("ERROR!! can not find start_blk and end_blk\n");
++		return -1;
++	}
++
++	block_offset = block - start_blk;
++	for (j = start_blk; j <= end_blk;j++) {
++		if (((chip->bbt[j >> 2] >> ((j<<1) & 0x6)) & 0x3) == 0x0) {
++			if (!block_offset)
++				break;
++			block_offset--;
++		} else {
++			bad_block++;
++		}
++	}
++	if (j <= end_blk) {
++		return j;
++	} else {
++		// remap to the bad block
++		for (j = end_blk; bad_block > 0; j--)
++		{
++			if (((chip->bbt[j >> 2] >> ((j<<1) & 0x6)) & 0x3) != 0x0)
++			{
++				bad_block--;
++				if (bad_block <= block_offset)
++					return j;
++			}
++		}
++	}
++
++	printk("Error!! block_remap error\n");
++	return -1;
++}
++
++int
++check_block_remap(struct mtd_info *mtd, int block)
++{
++	if (shift_on_bbt)
++		return  block_remap(mtd, block);
++	else
++		return block;
++}
++EXPORT_SYMBOL(check_block_remap);
++
++
++static int
++write_next_on_fail(struct mtd_info *mtd, char *write_buf, int page, int * to_blk)
++{
++	struct nand_chip *chip = mtd->priv;
++	int i, j, to_page = 0, first_page;
++	char *buf, *oob;
++	int start_blk = 0, end_blk;
++	int mapped_block;
++	int page_per_block_bit = chip->phys_erase_shift - chip->page_shift;
++	int block = page >> page_per_block_bit;
++
++	// find next available block in the same MTD partition 
++	mapped_block = block_remap(mtd, block);
++	if (mapped_block == -1)
++		return NAND_STATUS_FAIL;
++
++	get_start_end_block(mtd, block, &start_blk, &end_blk);
++
++	buf = kzalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL | GFP_DMA);
++	if (buf == NULL)
++		return -1;
++
++	oob = buf + mtd->writesize;
++	for ((*to_blk) = block + 1; (*to_blk) <= end_blk ; (*to_blk)++)	{
++		if (nand_bbt_get(mtd, (*to_blk) << page_per_block_bit) == 0) {
++			int status;
++			status = mtk_nand_erase_hw(mtd, (*to_blk) << page_per_block_bit);
++			if (status & NAND_STATUS_FAIL)	{
++				mtk_nand_block_markbad_hw(mtd, (*to_blk) << chip->phys_erase_shift);
++				nand_bbt_set(mtd, (*to_blk) << page_per_block_bit, 0x3);
++			} else {
++				/* good block */
++				to_page = (*to_blk) << page_per_block_bit;
++				break;
++			}
++		}
++	}
++
++	if (!to_page) {
++		kfree(buf);
++		return -1;
++	}
++
++	first_page = (page >> page_per_block_bit) << page_per_block_bit;
++	for (i = 0; i < (1 << page_per_block_bit); i++) {
++		if ((first_page + i) != page) {
++			mtk_nand_read_oob_hw(mtd, chip, (first_page+i));
++			for (j = 0; j < mtd->oobsize; j++)
++				if (chip->oob_poi[j] != (unsigned char)0xff)
++					break;
++			if (j < mtd->oobsize)	{
++				mtk_nand_exec_read_page(mtd, (first_page+i), mtd->writesize, buf, oob);
++				memset(oob, 0xff, mtd->oobsize);
++				if (mtk_nand_exec_write_page(mtd, to_page + i, mtd->writesize, (u8 *)buf, oob) != 0) {
++					int ret, new_blk = 0;
++					nand_bbt_set(mtd, to_page, 0x3);
++					ret =  write_next_on_fail(mtd, buf, to_page + i, &new_blk);
++					if (ret) {
++						kfree(buf);
++						mtk_nand_block_markbad_hw(mtd, to_page << chip->page_shift);
++						return ret;
++					}
++					mtk_nand_block_markbad_hw(mtd, to_page << chip->page_shift);
++					*to_blk = new_blk;
++					to_page = ((*to_blk) <<  page_per_block_bit);
++				}
++			}
++		} else {
++			memset(chip->oob_poi, 0xff, mtd->oobsize);
++			if (mtk_nand_exec_write_page(mtd, to_page + i, mtd->writesize, (u8 *)write_buf, chip->oob_poi) != 0) {
++				int ret, new_blk = 0;
++				nand_bbt_set(mtd, to_page, 0x3);
++				ret =  write_next_on_fail(mtd, write_buf, to_page + i, &new_blk);
++				if (ret) {
++					kfree(buf);
++					mtk_nand_block_markbad_hw(mtd, to_page << chip->page_shift);
++					return ret;
++				}
++				mtk_nand_block_markbad_hw(mtd, to_page << chip->page_shift);
++				*to_blk = new_blk;
++				to_page = ((*to_blk) <<  page_per_block_bit);
++			}
++		}
++	}
++
++	kfree(buf);
++
++	return 0;
++}
++
++static int
++mtk_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, uint32_t offset,
++		int data_len, const u8 * buf, int oob_required, int page, int cached, int raw)
++{
++	int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
++	int block = page / page_per_block;
++	u16 page_in_block = page % page_per_block;
++	int mapped_block = block;
++
++#if defined(MTK_NAND_BMT)
++	mapped_block = get_mapping_block_index(block);
++	// write bad index into oob
++	if (mapped_block != block)
++		set_bad_index_to_oob(chip->oob_poi, block);
++	else
++		set_bad_index_to_oob(chip->oob_poi, FAKE_INDEX);
++#else
++	if (shift_on_bbt) {
++		mapped_block = block_remap(mtd, block);
++		if (mapped_block == -1)
++			return NAND_STATUS_FAIL;
++		if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
++			return NAND_STATUS_FAIL;
++	}
++#endif
++	do {
++		if (mtk_nand_exec_write_page(mtd, page_in_block + mapped_block * page_per_block, mtd->writesize, (u8 *)buf, chip->oob_poi)) {
++			MSG(INIT, "write fail at block: 0x%x, page: 0x%x\n", mapped_block, page_in_block);
++#if defined(MTK_NAND_BMT)
++			if (update_bmt((page_in_block + mapped_block * page_per_block) << chip->page_shift, UPDATE_WRITE_FAIL, (u8 *) buf, chip->oob_poi)) {
++				MSG(INIT, "Update BMT success\n");
++				return 0;
++			} else {
++				MSG(INIT, "Update BMT fail\n");
++				return -EIO;
++			}
++#else
++			{
++				int new_blk;
++				nand_bbt_set(mtd, page_in_block + mapped_block * page_per_block, 0x3);
++				if (write_next_on_fail(mtd, (char *)buf, page_in_block + mapped_block * page_per_block, &new_blk) != 0)
++				{
++				mtk_nand_block_markbad_hw(mtd, (page_in_block + mapped_block * page_per_block) << chip->page_shift);
++				return NAND_STATUS_FAIL;
++				}
++				mtk_nand_block_markbad_hw(mtd, (page_in_block + mapped_block * page_per_block) << chip->page_shift);
++				break;
++			}
++#endif
++		} else
++			break;
++	} while(1);
++
++	return 0;
++}
++
++static void
++mtk_nand_command_bp(struct mtd_info *mtd, unsigned int command, int column, int page_addr)
++{
++	struct nand_chip *nand = mtd->priv;
++
++	switch (command) {
++	case NAND_CMD_SEQIN:
++		memset(g_kCMD.au1OOB, 0xFF, sizeof(g_kCMD.au1OOB));
++		g_kCMD.pDataBuf = NULL;
++		g_kCMD.u4RowAddr = page_addr;
++		g_kCMD.u4ColAddr = column;
++		break;
++
++	case NAND_CMD_PAGEPROG:
++		if (g_kCMD.pDataBuf || (0xFF != g_kCMD.au1OOB[nand_badblock_offset])) {
++			u8 *pDataBuf = g_kCMD.pDataBuf ? g_kCMD.pDataBuf : nand->buffers->databuf;
++			mtk_nand_exec_write_page(mtd, g_kCMD.u4RowAddr, mtd->writesize, pDataBuf, g_kCMD.au1OOB);
++			g_kCMD.u4RowAddr = (u32) - 1;
++			g_kCMD.u4OOBRowAddr = (u32) - 1;
++		}
++		break;
++
++	case NAND_CMD_READOOB:
++		g_kCMD.u4RowAddr = page_addr;
++		g_kCMD.u4ColAddr = column + mtd->writesize;
++		break;
++
++	case NAND_CMD_READ0:
++		g_kCMD.u4RowAddr = page_addr;
++		g_kCMD.u4ColAddr = column;
++		break;
++
++	case NAND_CMD_ERASE1:
++		nand->state=FL_ERASING;
++		(void)mtk_nand_reset();
++		mtk_nand_set_mode(CNFG_OP_ERASE);
++		(void)mtk_nand_set_command(NAND_CMD_ERASE1);
++		(void)mtk_nand_set_address(0, page_addr, 0, devinfo.addr_cycle - 2);
++		break;
++
++	case NAND_CMD_ERASE2:
++		(void)mtk_nand_set_command(NAND_CMD_ERASE2);
++		while (DRV_Reg32(NFI_STA_REG32) & STA_NAND_BUSY)
++			;
++		break;
++
++	case NAND_CMD_STATUS:
++		(void)mtk_nand_reset();
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
++		mtk_nand_set_mode(CNFG_OP_SRD);
++		mtk_nand_set_mode(CNFG_READ_EN);
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++		(void)mtk_nand_set_command(NAND_CMD_STATUS);
++		NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_NOB_MASK);
++		mb();
++		DRV_WriteReg16(NFI_CON_REG16, CON_NFI_SRD | (1 << CON_NFI_NOB_SHIFT));
++		g_bcmdstatus = true;
++		break;
++
++	case NAND_CMD_RESET:
++		(void)mtk_nand_reset();
++		DRV_WriteReg16(NFI_INTR_EN_REG16, INTR_RST_DONE_EN);
++		(void)mtk_nand_set_command(NAND_CMD_RESET);
++		DRV_WriteReg16(NFI_BASE+0x44, 0xF1);
++		while(!(DRV_Reg16(NFI_INTR_REG16)&INTR_RST_DONE_EN))
++			;
++		break;
++
++	case NAND_CMD_READID:
++		mtk_nand_reset();
++		/* Disable HW ECC */
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
++		NFI_SET_REG16(NFI_CNFG_REG16, CNFG_READ_EN | CNFG_BYTE_RW);
++		(void)mtk_nand_reset();
++		mb();
++		mtk_nand_set_mode(CNFG_OP_SRD);
++		(void)mtk_nand_set_command(NAND_CMD_READID);
++		(void)mtk_nand_set_address(0, 0, 1, 0);
++		DRV_WriteReg16(NFI_CON_REG16, CON_NFI_SRD);
++		while (DRV_Reg32(NFI_STA_REG32) & STA_DATAR_STATE)
++			;
++		break;
++
++	default:
++		BUG();
++		break;
++	}
++}
++
++static void
++mtk_nand_select_chip(struct mtd_info *mtd, int chip)
++{
++	if ((chip == -1) && (false == g_bInitDone)) {
++		struct nand_chip *nand = mtd->priv;
++		struct mtk_nand_host *host = nand->priv;
++		struct mtk_nand_host_hw *hw = host->hw;
++		u32 spare_per_sector = mtd->oobsize / (mtd->writesize / 512);
++		u32 ecc_bit = 4;
++		u32 spare_bit = PAGEFMT_SPARE_16;
++
++		if (spare_per_sector >= 28) {
++			spare_bit = PAGEFMT_SPARE_28;
++			ecc_bit = 12;
++			spare_per_sector = 28;
++		} else if (spare_per_sector >= 27) {
++			spare_bit = PAGEFMT_SPARE_27;
++			ecc_bit = 8;
++			spare_per_sector = 27;
++		} else if (spare_per_sector >= 26) {
++			spare_bit = PAGEFMT_SPARE_26;
++			ecc_bit = 8;
++			spare_per_sector = 26;
++		} else if (spare_per_sector >= 16) {
++			spare_bit = PAGEFMT_SPARE_16;
++			ecc_bit = 4;
++			spare_per_sector = 16;
++		} else {
++			MSG(INIT, "[NAND]: NFI not support oobsize: %x\n", spare_per_sector);
++			ASSERT(0);
++		}
++		mtd->oobsize = spare_per_sector*(mtd->writesize/512);
++		MSG(INIT, "[NAND]select ecc bit:%d, sparesize :%d spare_per_sector=%d\n",ecc_bit,mtd->oobsize,spare_per_sector);
++		/* Setup PageFormat */
++		if (4096 == mtd->writesize) {
++			NFI_SET_REG16(NFI_PAGEFMT_REG16, (spare_bit << PAGEFMT_SPARE_SHIFT) | PAGEFMT_4K);
++			nand->cmdfunc = mtk_nand_command_bp;
++		} else if (2048 == mtd->writesize) {
++			NFI_SET_REG16(NFI_PAGEFMT_REG16, (spare_bit << PAGEFMT_SPARE_SHIFT) | PAGEFMT_2K);
++			nand->cmdfunc = mtk_nand_command_bp;
++		}
++		ECC_Config(hw,ecc_bit);
++		g_bInitDone = true;
++	}
++	switch (chip) {
++	case -1:
++		break;
++	case 0:
++	case 1:
++		/*  Jun Shen, 2011.04.13  */
++		/* Note: MT6577 EVB NAND  is mounted on CS0, but FPGA is CS1  */
++		DRV_WriteReg16(NFI_CSEL_REG16, chip);
++		/*  Jun Shen, 2011.04.13 */
++		break;
++	}
++}
++
++static uint8_t
++mtk_nand_read_byte(struct mtd_info *mtd)
++{
++	uint8_t retval = 0;
++
++	if (!mtk_nand_pio_ready()) {
++		printk("pio ready timeout\n");
++		retval = false;
++	}
++
++	if (g_bcmdstatus) {
++		retval = DRV_Reg8(NFI_DATAR_REG32);
++		NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_NOB_MASK);
++		mtk_nand_reset();
++		if (g_bHwEcc) {
++			NFI_SET_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++		} else {
++			NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++		}
++		g_bcmdstatus = false;
++	} else
++		retval = DRV_Reg8(NFI_DATAR_REG32);
++
++	return retval;
++}
++
++static void
++mtk_nand_read_buf(struct mtd_info *mtd, uint8_t * buf, int len)
++{
++	struct nand_chip *nand = (struct nand_chip *)mtd->priv;
++	struct NAND_CMD *pkCMD = &g_kCMD;
++	u32 u4ColAddr = pkCMD->u4ColAddr;
++	u32 u4PageSize = mtd->writesize;
++
++	if (u4ColAddr < u4PageSize) {
++		if ((u4ColAddr == 0) && (len >= u4PageSize)) {
++			mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, buf, pkCMD->au1OOB);
++			if (len > u4PageSize) {
++				u32 u4Size = min(len - u4PageSize, sizeof(pkCMD->au1OOB));
++				memcpy(buf + u4PageSize, pkCMD->au1OOB, u4Size);
++			}
++		} else {
++			mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, nand->buffers->databuf, pkCMD->au1OOB);
++			memcpy(buf, nand->buffers->databuf + u4ColAddr, len);
++		}
++		pkCMD->u4OOBRowAddr = pkCMD->u4RowAddr;
++	} else {
++		u32 u4Offset = u4ColAddr - u4PageSize;
++		u32 u4Size = min(len - u4Offset, sizeof(pkCMD->au1OOB));
++		if (pkCMD->u4OOBRowAddr != pkCMD->u4RowAddr) {
++			mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, nand->buffers->databuf, pkCMD->au1OOB);
++			pkCMD->u4OOBRowAddr = pkCMD->u4RowAddr;
++		}
++		memcpy(buf, pkCMD->au1OOB + u4Offset, u4Size);
++	}
++	pkCMD->u4ColAddr += len;
++}
++
++static void
++mtk_nand_write_buf(struct mtd_info *mtd, const uint8_t * buf, int len)
++{
++	struct NAND_CMD *pkCMD = &g_kCMD;
++	u32 u4ColAddr = pkCMD->u4ColAddr;
++	u32 u4PageSize = mtd->writesize;
++	int i4Size, i;
++
++	if (u4ColAddr >= u4PageSize) {
++		u32 u4Offset = u4ColAddr - u4PageSize;
++		u8 *pOOB = pkCMD->au1OOB + u4Offset;
++		i4Size = min(len, (int)(sizeof(pkCMD->au1OOB) - u4Offset));
++		for (i = 0; i < i4Size; i++) {
++			pOOB[i] &= buf[i];
++		}
++	} else {
++		pkCMD->pDataBuf = (u8 *) buf;
++	}
++
++	pkCMD->u4ColAddr += len;
++}
++
++static int
++mtk_nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t * buf, int oob_required)
++{
++	mtk_nand_write_buf(mtd, buf, mtd->writesize);
++	mtk_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
++	return 0;
++}
++
++static int
++mtk_nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf, int oob_required, int page)
++{
++	struct NAND_CMD *pkCMD = &g_kCMD;
++	u32 u4ColAddr = pkCMD->u4ColAddr;
++	u32 u4PageSize = mtd->writesize;
++
++	if (u4ColAddr == 0) {
++		mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, buf, chip->oob_poi);
++		pkCMD->u4ColAddr += u4PageSize + mtd->oobsize;
++	}
++
++	return 0;
++}
++
++static int
++mtk_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, u8 * buf, int page)
++{
++	int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
++	int block = page / page_per_block;
++	u16 page_in_block = page % page_per_block;
++	int mapped_block = block;
++
++#if defined (MTK_NAND_BMT)
++	mapped_block = get_mapping_block_index(block);
++	if (mtk_nand_exec_read_page(mtd, page_in_block + mapped_block * page_per_block,
++			mtd->writesize, buf, chip->oob_poi))
++		return 0;
++#else
++	if (shift_on_bbt) {
++		mapped_block = block_remap(mtd, block);
++		if (mapped_block == -1)
++			return NAND_STATUS_FAIL;
++		if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
++			return NAND_STATUS_FAIL;
++	}
++
++	if (mtk_nand_exec_read_page(mtd, page_in_block + mapped_block * page_per_block, mtd->writesize, buf, chip->oob_poi))
++		return 0;
++	else
++		return -EIO;
++#endif
++}
++
++int
++mtk_nand_erase_hw(struct mtd_info *mtd, int page)
++{
++	struct nand_chip *chip = (struct nand_chip *)mtd->priv;
++
++	chip->erase_cmd(mtd, page);
++
++	return chip->waitfunc(mtd, chip);
++}
++
++static int
++mtk_nand_erase(struct mtd_info *mtd, int page)
++{
++	// get mapping 
++	struct nand_chip *chip = mtd->priv;
++	int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
++	int page_in_block = page % page_per_block;
++	int block = page / page_per_block;
++	int mapped_block = block;
++
++#if defined(MTK_NAND_BMT)    
++	mapped_block = get_mapping_block_index(block);
++#else
++	if (shift_on_bbt) {
++		mapped_block = block_remap(mtd, block);
++		if (mapped_block == -1)
++			return NAND_STATUS_FAIL;
++		if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
++			return NAND_STATUS_FAIL;
++	}
++#endif
++
++	do {
++		int status = mtk_nand_erase_hw(mtd, page_in_block + page_per_block * mapped_block);
++
++		if (status & NAND_STATUS_FAIL) {
++#if defined (MTK_NAND_BMT)    	
++			if (update_bmt( (page_in_block + mapped_block * page_per_block) << chip->page_shift,
++					UPDATE_ERASE_FAIL, NULL, NULL))
++			{
++				MSG(INIT, "Erase fail at block: 0x%x, update BMT success\n", mapped_block);
++				return 0;
++			} else {
++				MSG(INIT, "Erase fail at block: 0x%x, update BMT fail\n", mapped_block);
++				return NAND_STATUS_FAIL;
++			}
++#else
++			mtk_nand_block_markbad_hw(mtd, (page_in_block + mapped_block * page_per_block) << chip->page_shift);
++			nand_bbt_set(mtd, page_in_block + mapped_block * page_per_block, 0x3);
++			if (shift_on_bbt) {
++				mapped_block = block_remap(mtd, block);
++				if (mapped_block == -1)
++					return NAND_STATUS_FAIL;
++				if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
++					return NAND_STATUS_FAIL;
++			} else
++				return NAND_STATUS_FAIL;
++#endif
++		} else
++			break;
++	} while(1);
++
++	return 0;
++}
++
++static int
++mtk_nand_read_oob_raw(struct mtd_info *mtd, uint8_t * buf, int page_addr, int len)
++{
++	struct nand_chip *chip = (struct nand_chip *)mtd->priv;
++	u32 col_addr = 0;
++	u32 sector = 0;
++	int res = 0;
++	u32 colnob = 2, rawnob = devinfo.addr_cycle - 2;
++	int randomread = 0;
++	int read_len = 0;
++	int sec_num = 1<<(chip->page_shift-9);
++	int spare_per_sector = mtd->oobsize/sec_num;
++
++	if (len >  NAND_MAX_OOBSIZE || len % OOB_AVAI_PER_SECTOR || !buf) {
++		printk(KERN_WARNING "[%s] invalid parameter, len: %d, buf: %p\n", __FUNCTION__, len, buf);
++		return -EINVAL;
++	}
++	if (len > spare_per_sector)
++		randomread = 1;
++	if (!randomread || !(devinfo.advancedmode & RAMDOM_READ)) {
++		while (len > 0) {
++			read_len = min(len, spare_per_sector);
++			col_addr = NAND_SECTOR_SIZE + sector * (NAND_SECTOR_SIZE + spare_per_sector); // TODO: Fix this hard-code 16
++			if (!mtk_nand_ready_for_read(chip, page_addr, col_addr, false, NULL)) {
++				printk(KERN_WARNING "mtk_nand_ready_for_read return failed\n");
++				res = -EIO;
++				goto error;
++			}
++			if (!mtk_nand_mcu_read_data(buf + spare_per_sector * sector, read_len)) {
++				printk(KERN_WARNING "mtk_nand_mcu_read_data return failed\n");
++				res = -EIO;
++				goto error;
++			}
++			mtk_nand_check_RW_count(read_len);
++			mtk_nand_stop_read();
++			sector++;
++			len -= read_len;
++		}
++	} else {
++		col_addr = NAND_SECTOR_SIZE;
++		if (chip->options & NAND_BUSWIDTH_16)
++			col_addr /= 2;
++		if (!mtk_nand_reset())
++			goto error;
++		mtk_nand_set_mode(0x6000);
++		NFI_SET_REG16(NFI_CNFG_REG16, CNFG_READ_EN);
++		DRV_WriteReg16(NFI_CON_REG16, 4 << CON_NFI_SEC_SHIFT);
++
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
++		NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++
++		mtk_nand_set_autoformat(false);
++
++		if (!mtk_nand_set_command(NAND_CMD_READ0))
++			goto error;
++		//1 FIXED ME: For Any Kind of AddrCycle
++		if (!mtk_nand_set_address(col_addr, page_addr, colnob, rawnob))
++			goto error;
++		if (!mtk_nand_set_command(NAND_CMD_READSTART))
++			goto error;
++		if (!mtk_nand_status_ready(STA_NAND_BUSY))
++			goto error;
++		read_len = min(len, spare_per_sector);
++		if (!mtk_nand_mcu_read_data(buf + spare_per_sector * sector, read_len)) {
++			printk(KERN_WARNING "mtk_nand_mcu_read_data return failed first 16\n");
++			res = -EIO;
++			goto error;
++		}
++		sector++;
++		len -= read_len;
++		mtk_nand_stop_read();
++		while (len > 0) {
++			read_len = min(len,  spare_per_sector);
++			if (!mtk_nand_set_command(0x05))
++				goto error;
++			col_addr = NAND_SECTOR_SIZE + sector * (NAND_SECTOR_SIZE + spare_per_sector);
++			if (chip->options & NAND_BUSWIDTH_16)
++				col_addr /= 2;
++			DRV_WriteReg32(NFI_COLADDR_REG32, col_addr);
++			DRV_WriteReg16(NFI_ADDRNOB_REG16, 2);
++			DRV_WriteReg16(NFI_CON_REG16, 4 << CON_NFI_SEC_SHIFT);
++			if (!mtk_nand_status_ready(STA_ADDR_STATE))
++				goto error;
++			if (!mtk_nand_set_command(0xE0))
++				goto error;
++			if (!mtk_nand_status_ready(STA_NAND_BUSY))
++				goto error;
++			if (!mtk_nand_mcu_read_data(buf + spare_per_sector * sector, read_len)) {
++				printk(KERN_WARNING "mtk_nand_mcu_read_data return failed first 16\n");
++				res = -EIO;
++				goto error;
++			}
++			mtk_nand_stop_read();
++			sector++;
++			len -= read_len;
++		}
++	}
++error:
++	NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_BRD);
++	return res;
++}
++
++static int
++mtk_nand_write_oob_raw(struct mtd_info *mtd, const uint8_t * buf, int page_addr, int len)
++{
++	struct nand_chip *chip = mtd->priv;
++	u32 col_addr = 0;
++	u32 sector = 0;
++	int write_len = 0;
++	int status;
++	int sec_num = 1<<(chip->page_shift-9);
++	int spare_per_sector = mtd->oobsize/sec_num;
++
++	if (len >  NAND_MAX_OOBSIZE || len % OOB_AVAI_PER_SECTOR || !buf) {
++		printk(KERN_WARNING "[%s] invalid parameter, len: %d, buf: %p\n", __FUNCTION__, len, buf);
++		return -EINVAL;
++	}
++
++	while (len > 0) {
++		write_len = min(len,  spare_per_sector);
++		col_addr = sector * (NAND_SECTOR_SIZE +  spare_per_sector) + NAND_SECTOR_SIZE;
++		if (!mtk_nand_ready_for_write(chip, page_addr, col_addr, false, NULL))
++			return -EIO;
++		if (!mtk_nand_mcu_write_data(mtd, buf + sector * spare_per_sector, write_len))
++			return -EIO;
++		(void)mtk_nand_check_RW_count(write_len);
++		NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_BWR);
++		(void)mtk_nand_set_command(NAND_CMD_PAGEPROG);
++		while (DRV_Reg32(NFI_STA_REG32) & STA_NAND_BUSY)
++			;
++		status = chip->waitfunc(mtd, chip);
++		if (status & NAND_STATUS_FAIL) {
++			printk(KERN_INFO "status: %d\n", status);
++			return -EIO;
++		}
++		len -= write_len;
++		sector++;
++	}
++
++	return 0;
++}
++
++static int
++mtk_nand_write_oob_hw(struct mtd_info *mtd, struct nand_chip *chip, int page)
++{
++	int i, iter;
++	int sec_num = 1<<(chip->page_shift-9);
++	int spare_per_sector = mtd->oobsize/sec_num;
++
++	memcpy(local_oob_buf, chip->oob_poi, mtd->oobsize);
++
++	// copy ecc data
++	for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
++		iter = (i / (spare_per_sector-OOB_AVAI_PER_SECTOR)) *  spare_per_sector + OOB_AVAI_PER_SECTOR + i % (spare_per_sector-OOB_AVAI_PER_SECTOR);
++		local_oob_buf[iter] = chip->oob_poi[chip->ecc.layout->eccpos[i]];
++	}
++
++	// copy FDM data
++	for (i = 0; i < sec_num; i++)
++		memcpy(&local_oob_buf[i * spare_per_sector], &chip->oob_poi[i * OOB_AVAI_PER_SECTOR], OOB_AVAI_PER_SECTOR);
++
++	return mtk_nand_write_oob_raw(mtd, local_oob_buf, page, mtd->oobsize);
++}
++
++static int mtk_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
++{
++	int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
++	int block = page / page_per_block;
++	u16 page_in_block = page % page_per_block;
++	int mapped_block = block;
++
++#if defined(MTK_NAND_BMT)
++	mapped_block = get_mapping_block_index(block);
++	// write bad index into oob
++	if (mapped_block != block)
++		set_bad_index_to_oob(chip->oob_poi, block);
++	else
++		set_bad_index_to_oob(chip->oob_poi, FAKE_INDEX);
++#else
++	if (shift_on_bbt)
++	{
++		mapped_block = block_remap(mtd, block);
++		if (mapped_block == -1)
++			return NAND_STATUS_FAIL;
++		if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
++			return NAND_STATUS_FAIL;
++	}
++#endif
++	do {
++		if (mtk_nand_write_oob_hw(mtd, chip, page_in_block + mapped_block * page_per_block /* page */)) {
++			MSG(INIT, "write oob fail at block: 0x%x, page: 0x%x\n", mapped_block, page_in_block);
++#if defined(MTK_NAND_BMT)      
++			if (update_bmt((page_in_block + mapped_block * page_per_block) << chip->page_shift,
++					UPDATE_WRITE_FAIL, NULL, chip->oob_poi))
++			{
++				MSG(INIT, "Update BMT success\n");
++				return 0;
++			} else {
++				MSG(INIT, "Update BMT fail\n");
++				return -EIO;
++			}
++#else
++			mtk_nand_block_markbad_hw(mtd, (page_in_block + mapped_block * page_per_block) << chip->page_shift);
++			nand_bbt_set(mtd, page_in_block + mapped_block * page_per_block, 0x3);
++			if (shift_on_bbt) {
++				mapped_block = block_remap(mtd, mapped_block);
++				if (mapped_block == -1)
++					return NAND_STATUS_FAIL;
++				if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
++					return NAND_STATUS_FAIL;
++			} else {
++				return NAND_STATUS_FAIL;
++			}
++#endif
++		} else
++			break;
++	} while (1);
++
++	return 0;
++}
++
++int
++mtk_nand_block_markbad_hw(struct mtd_info *mtd, loff_t offset)
++{
++	struct nand_chip *chip = mtd->priv;
++	int block = (int)offset >> chip->phys_erase_shift;
++	int page = block * (1 << (chip->phys_erase_shift - chip->page_shift));
++	u8 buf[8];
++
++	memset(buf, 0xFF, 8);
++	buf[0] = 0;
++	return  mtk_nand_write_oob_raw(mtd, buf, page, 8);
++}
++
++static int
++mtk_nand_block_markbad(struct mtd_info *mtd, loff_t offset)
++{
++	struct nand_chip *chip = mtd->priv;
++	int block = (int)offset >> chip->phys_erase_shift;
++	int ret;
++	int mapped_block = block;
++
++	nand_get_device(chip, mtd, FL_WRITING);
++
++#if defined(MTK_NAND_BMT)    
++	mapped_block = get_mapping_block_index(block);
++	ret = mtk_nand_block_markbad_hw(mtd, mapped_block << chip->phys_erase_shift);
++#else
++	if (shift_on_bbt) {
++		mapped_block = block_remap(mtd, block);
++		if (mapped_block == -1) {
++			printk("NAND mark bad failed\n");
++			nand_release_device(mtd);
++			return NAND_STATUS_FAIL;
++		}
++	}
++	ret = mtk_nand_block_markbad_hw(mtd, mapped_block << chip->phys_erase_shift);
++#endif
++	nand_release_device(mtd);
++
++	return ret;
++}
++
++int
++mtk_nand_read_oob_hw(struct mtd_info *mtd, struct nand_chip *chip, int page)
++{
++	int i;
++	u8 iter = 0;
++
++	int sec_num = 1<<(chip->page_shift-9);
++	int spare_per_sector = mtd->oobsize/sec_num;
++
++	if (mtk_nand_read_oob_raw(mtd, chip->oob_poi, page, mtd->oobsize)) {
++		printk(KERN_ERR "[%s]mtk_nand_read_oob_raw return failed\n", __FUNCTION__);
++		return -EIO;
++	}
++
++	// adjust to ecc physical layout to memory layout
++	/*********************************************************/
++	/* FDM0 | ECC0 | FDM1 | ECC1 | FDM2 | ECC2 | FDM3 | ECC3 */
++	/*  8B  |  8B  |  8B  |  8B  |  8B  |  8B  |  8B  |  8B  */
++	/*********************************************************/
++
++	memcpy(local_oob_buf, chip->oob_poi, mtd->oobsize);
++	// copy ecc data
++	for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
++		iter = (i / (spare_per_sector-OOB_AVAI_PER_SECTOR)) *  spare_per_sector + OOB_AVAI_PER_SECTOR + i % (spare_per_sector-OOB_AVAI_PER_SECTOR);
++		chip->oob_poi[chip->ecc.layout->eccpos[i]] = local_oob_buf[iter];
++	}
++
++	// copy FDM data
++	for (i = 0; i < sec_num; i++) {
++		memcpy(&chip->oob_poi[i * OOB_AVAI_PER_SECTOR], &local_oob_buf[i *  spare_per_sector], OOB_AVAI_PER_SECTOR);
++	}
++
++	return 0;
++}
++
++static int
++mtk_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
++{
++	int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
++	int block = page / page_per_block;
++	u16 page_in_block = page % page_per_block;
++	int mapped_block = block;
++
++#if defined (MTK_NAND_BMT)
++	mapped_block = get_mapping_block_index(block);
++	mtk_nand_read_oob_hw(mtd, chip, page_in_block + mapped_block * page_per_block);
++#else
++	if (shift_on_bbt) {
++		mapped_block = block_remap(mtd, block);
++		if (mapped_block == -1)
++			return NAND_STATUS_FAIL;
++		// allow to read oob even if the block is bad
++	}
++	if (mtk_nand_read_oob_hw(mtd, chip, page_in_block + mapped_block * page_per_block)!=0)
++		return -1;
++#endif
++	return 0;
++}
++
++int
++mtk_nand_block_bad_hw(struct mtd_info *mtd, loff_t ofs)
++{
++	struct nand_chip *chip = (struct nand_chip *)mtd->priv;
++	int page_addr = (int)(ofs >> chip->page_shift);
++	unsigned int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
++	unsigned char oob_buf[8];
++
++	page_addr &= ~(page_per_block - 1);
++	if (mtk_nand_read_oob_raw(mtd, oob_buf, page_addr, sizeof(oob_buf))) {
++		printk(KERN_WARNING "mtk_nand_read_oob_raw return error\n");
++		return 1;
++	}
++
++	if (oob_buf[0] != 0xff) {
++		printk(KERN_WARNING "Bad block detected at 0x%x, oob_buf[0] is 0x%x\n", page_addr, oob_buf[0]);
++		// dump_nfi();
++		return 1;
++	}
++
++	return 0;
++}
++
++static int
++mtk_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
++{
++	int chipnr = 0;
++	struct nand_chip *chip = (struct nand_chip *)mtd->priv;
++	int block = (int)ofs >> chip->phys_erase_shift;
++	int mapped_block = block;
++	int ret;
++
++	if (getchip) {
++		chipnr = (int)(ofs >> chip->chip_shift);
++		nand_get_device(chip, mtd, FL_READING);
++		/* Select the NAND device */
++		chip->select_chip(mtd, chipnr);
++	}
++
++#if defined(MTK_NAND_BMT)    
++	mapped_block = get_mapping_block_index(block);
++#else
++	if (shift_on_bbt) {
++		mapped_block = block_remap(mtd, block);
++		if (mapped_block == -1) {
++		if (getchip)
++			nand_release_device(mtd);
++			return NAND_STATUS_FAIL;
++		}
++	}
++#endif
++
++	ret = mtk_nand_block_bad_hw(mtd, mapped_block << chip->phys_erase_shift);
++#if defined (MTK_NAND_BMT)	
++	if (ret) {
++		MSG(INIT, "Unmapped bad block: 0x%x\n", mapped_block);
++		if (update_bmt(mapped_block << chip->phys_erase_shift, UPDATE_UNMAPPED_BLOCK, NULL, NULL)) {
++			MSG(INIT, "Update BMT success\n");
++			ret = 0;
++		} else {
++			MSG(INIT, "Update BMT fail\n");
++			ret = 1;
++		}
++	}
++#endif
++
++	if (getchip)
++		nand_release_device(mtd);
++
++	return ret;
++}
++
++#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
++char gacBuf[4096 + 288];
++
++static int
++mtk_nand_verify_buf(struct mtd_info *mtd, const uint8_t * buf, int len)
++{
++	struct nand_chip *chip = (struct nand_chip *)mtd->priv;
++	struct NAND_CMD *pkCMD = &g_kCMD;
++	u32 u4PageSize = mtd->writesize;
++	u32 *pSrc, *pDst;
++	int i;
++
++	mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, gacBuf, gacBuf + u4PageSize);
++
++	pSrc = (u32 *) buf;
++	pDst = (u32 *) gacBuf;
++	len = len / sizeof(u32);
++	for (i = 0; i < len; ++i) {
++		if (*pSrc != *pDst) {
++			MSG(VERIFY, "mtk_nand_verify_buf page fail at page %d\n", pkCMD->u4RowAddr);
++			return -1;
++		}
++		pSrc++;
++		pDst++;
++	}
++
++	pSrc = (u32 *) chip->oob_poi;
++	pDst = (u32 *) (gacBuf + u4PageSize);
++
++	if ((pSrc[0] != pDst[0]) || (pSrc[1] != pDst[1]) || (pSrc[2] != pDst[2]) || (pSrc[3] != pDst[3]) || (pSrc[4] != pDst[4]) || (pSrc[5] != pDst[5])) {
++	// TODO: Ask Designer Why?
++	//(pSrc[6] != pDst[6]) || (pSrc[7] != pDst[7])) 
++		MSG(VERIFY, "mtk_nand_verify_buf oob fail at page %d\n", pkCMD->u4RowAddr);
++		MSG(VERIFY, "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", pSrc[0], pSrc[1], pSrc[2], pSrc[3], pSrc[4], pSrc[5], pSrc[6], pSrc[7]);
++		MSG(VERIFY, "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", pDst[0], pDst[1], pDst[2], pDst[3], pDst[4], pDst[5], pDst[6], pDst[7]);
++		return -1;
++	}
++	return 0;
++}
++#endif
++
++static void
++mtk_nand_init_hw(struct mtk_nand_host *host) {
++	struct mtk_nand_host_hw *hw = host->hw;
++	u32 data;
++
++	data = DRV_Reg32(RALINK_SYSCTL_BASE+0x60);
++	data &= ~((0x3<<18)|(0x3<<16));
++	data |= ((0x2<<18) |(0x2<<16));
++	DRV_WriteReg32(RALINK_SYSCTL_BASE+0x60, data);
++
++	MSG(INIT, "Enable NFI Clock\n");
++	nand_enable_clock();
++
++	g_bInitDone = false;
++	g_kCMD.u4OOBRowAddr = (u32) - 1;
++
++	/* Set default NFI access timing control */
++	DRV_WriteReg32(NFI_ACCCON_REG32, hw->nfi_access_timing);
++	DRV_WriteReg16(NFI_CNFG_REG16, 0);
++	DRV_WriteReg16(NFI_PAGEFMT_REG16, 0);
++
++	/* Reset the state machine and data FIFO, because flushing FIFO */
++	(void)mtk_nand_reset();
++
++	/* Set the ECC engine */
++	if (hw->nand_ecc_mode == NAND_ECC_HW) {
++		MSG(INIT, "%s : Use HW ECC\n", MODULE_NAME);
++		if (g_bHwEcc)
++			NFI_SET_REG32(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
++		ECC_Config(host->hw,4);
++		mtk_nand_configure_fdm(8);
++		mtk_nand_configure_lock();
++	}
++
++	NFI_SET_REG16(NFI_IOCON_REG16, 0x47);
++}
++
++static int mtk_nand_dev_ready(struct mtd_info *mtd)
++{
++	return !(DRV_Reg32(NFI_STA_REG32) & STA_NAND_BUSY);
++}
++
++#define FACT_BBT_BLOCK_NUM  32 // use the latest 32 BLOCK for factory bbt table
++#define FACT_BBT_OOB_SIGNATURE  1
++#define FACT_BBT_SIGNATURE_LEN  7
++const u8 oob_signature[] = "mtknand";
++static u8 *fact_bbt = 0;
++static u32 bbt_size = 0;
++
++static int
++read_fact_bbt(struct mtd_info *mtd, unsigned int page)
++{
++	struct nand_chip *chip = mtd->priv;
++
++	// read oob
++	if (mtk_nand_read_oob_hw(mtd, chip, page)==0)
++	{
++		if (chip->oob_poi[nand_badblock_offset] != 0xFF)
++		{
++			printk("Bad Block on Page %x\n", page);
++			return -1;
++		}
++		if (memcmp(&chip->oob_poi[FACT_BBT_OOB_SIGNATURE], oob_signature, FACT_BBT_SIGNATURE_LEN) != 0)
++		{
++			printk("compare signature failed %x\n", page);
++			return -1;
++		}
++		if (mtk_nand_exec_read_page(mtd, page, mtd->writesize, chip->buffers->databuf, chip->oob_poi))
++		{
++			printk("Signature matched and data read!\n");
++			memcpy(fact_bbt, chip->buffers->databuf, (bbt_size <= mtd->writesize)? bbt_size:mtd->writesize);
++			return 0;
++		}
++
++	}
++	printk("failed at page %x\n", page);
++	return -1;
++}
++
++static int
++load_fact_bbt(struct mtd_info *mtd)
++{
++	struct nand_chip *chip = mtd->priv;
++	int i;
++	u32 total_block;
++
++	total_block = 1 << (chip->chip_shift - chip->phys_erase_shift);
++	bbt_size = total_block >> 2;
++
++	if ((!fact_bbt) && (bbt_size))
++		fact_bbt = (u8 *)kmalloc(bbt_size, GFP_KERNEL);
++	if (!fact_bbt)
++		return -1;
++
++	for (i = total_block - 1; i >= (total_block - FACT_BBT_BLOCK_NUM); i--)
++	{
++		if (read_fact_bbt(mtd, i << (chip->phys_erase_shift - chip->page_shift)) == 0)
++		{
++			printk("load_fact_bbt success %d\n", i);
++			return 0;
++		}
++
++	}
++	printk("load_fact_bbt failed\n");
++	return -1;
++}
++
++static int
++mtk_nand_probe(struct platform_device *pdev)
++{
++	struct mtd_part_parser_data ppdata;
++	struct mtk_nand_host_hw *hw;
++	struct mtd_info *mtd;
++	struct nand_chip *nand_chip;
++	u8 ext_id1, ext_id2, ext_id3;
++	int err = 0;
++	int id;
++	u32 ext_id;
++	int i;
++	u32 data;
++
++	data = DRV_Reg32(RALINK_SYSCTL_BASE+0x60);
++	data &= ~((0x3<<18)|(0x3<<16));
++	data |= ((0x2<<18) |(0x2<<16));
++	DRV_WriteReg32(RALINK_SYSCTL_BASE+0x60, data);
++
++	hw = &mt7621_nand_hw,
++	BUG_ON(!hw);
++	/* Allocate memory for the device structure (and zero it) */
++	host = kzalloc(sizeof(struct mtk_nand_host), GFP_KERNEL);
++	if (!host) {
++		MSG(INIT, "mtk_nand: failed to allocate device structure.\n");
++		return -ENOMEM;
++	}
++
++	/* Allocate memory for 16 byte aligned buffer */
++	local_buffer_16_align = local_buffer + 16 - ((u32) local_buffer % 16);
++	printk(KERN_INFO "Allocate 16 byte aligned buffer: %p\n", local_buffer_16_align);
++	host->hw = hw;
++
++	/* init mtd data structure */
++	nand_chip = &host->nand_chip;
++	nand_chip->priv = host;     /* link the private data structures */
++
++	mtd = &host->mtd;
++	mtd->priv = nand_chip;
++	mtd->owner = THIS_MODULE;
++	mtd->name  = "MT7621-NAND";
++
++	hw->nand_ecc_mode = NAND_ECC_HW;
++
++	/* Set address of NAND IO lines */
++	nand_chip->IO_ADDR_R = (void __iomem *)NFI_DATAR_REG32;
++	nand_chip->IO_ADDR_W = (void __iomem *)NFI_DATAW_REG32;
++	nand_chip->chip_delay = 20; /* 20us command delay time */
++	nand_chip->ecc.mode = hw->nand_ecc_mode;    /* enable ECC */
++	nand_chip->ecc.strength = 1;
++	nand_chip->read_byte = mtk_nand_read_byte;
++	nand_chip->read_buf = mtk_nand_read_buf;
++	nand_chip->write_buf = mtk_nand_write_buf;
++#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
++	nand_chip->verify_buf = mtk_nand_verify_buf;
++#endif
++	nand_chip->select_chip = mtk_nand_select_chip;
++	nand_chip->dev_ready = mtk_nand_dev_ready;
++	nand_chip->cmdfunc = mtk_nand_command_bp;
++	nand_chip->ecc.read_page = mtk_nand_read_page_hwecc;
++	nand_chip->ecc.write_page = mtk_nand_write_page_hwecc;
++
++	nand_chip->ecc.layout = &nand_oob_64;
++	nand_chip->ecc.size = hw->nand_ecc_size;    //2048
++	nand_chip->ecc.bytes = hw->nand_ecc_bytes;  //32
++
++	// For BMT, we need to revise driver architecture
++	nand_chip->write_page = mtk_nand_write_page;
++	nand_chip->ecc.write_oob = mtk_nand_write_oob;
++	nand_chip->block_markbad = mtk_nand_block_markbad;   // need to add nand_get_device()/nand_release_device().
++	//	nand_chip->erase = mtk_nand_erase;	
++	//    nand_chip->read_page = mtk_nand_read_page;
++	nand_chip->ecc.read_oob = mtk_nand_read_oob;
++	nand_chip->block_bad = mtk_nand_block_bad;
++
++	//Qwert:Add for Uboot
++	mtk_nand_init_hw(host);
++	/* Select the device */
++	nand_chip->select_chip(mtd, NFI_DEFAULT_CS);
++
++	/*
++	* Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
++	* after power-up
++	*/
++	nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
++
++	memset(&devinfo, 0 , sizeof(flashdev_info));
++
++	/* Send the command for reading device ID */
++
++	nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
++
++	/* Read manufacturer and device IDs */
++	manu_id = nand_chip->read_byte(mtd);
++	dev_id = nand_chip->read_byte(mtd);
++	id = dev_id | (manu_id << 8);
++	        ext_id1 = nand_chip->read_byte(mtd);
++		    ext_id2 = nand_chip->read_byte(mtd);
++		        ext_id3 = nand_chip->read_byte(mtd);
++			    ext_id = ext_id1 << 16 | ext_id2 << 8 | ext_id3;
++	if (!get_device_info(id, ext_id, &devinfo)) {
++		u32 chip_mode = RALINK_REG(RALINK_SYSCTL_BASE+0x010)&0x0F;
++		MSG(INIT, "Not Support this Device! \r\n");
++		memset(&devinfo, 0 , sizeof(flashdev_info));
++		MSG(INIT, "chip_mode=%08X\n",chip_mode);
++
++		/* apply bootstrap first */
++		devinfo.addr_cycle = 5;
++		devinfo.iowidth = 8;
++
++		switch (chip_mode) {
++		case 10:
++			devinfo.pagesize = 2048;
++			devinfo.sparesize = 128;
++			devinfo.totalsize = 128;
++			devinfo.blocksize = 128;
++			break;
++		case 11:
++			devinfo.pagesize = 4096;
++			devinfo.sparesize = 128;
++			devinfo.totalsize = 1024;
++			devinfo.blocksize = 256;
++			break;
++		case 12:
++			devinfo.pagesize = 4096;
++			devinfo.sparesize = 224;
++			devinfo.totalsize = 2048;
++			devinfo.blocksize = 512;
++			break;
++		default:
++		case 1:
++			devinfo.pagesize = 2048;
++			devinfo.sparesize = 64;
++			devinfo.totalsize = 128;
++			devinfo.blocksize = 128;
++			break;
++		}
++
++		devinfo.timmingsetting = NFI_DEFAULT_ACCESS_TIMING;
++		devinfo.devciename[0] = 'U';
++		devinfo.advancedmode = 0;
++	}
++	mtd->writesize = devinfo.pagesize;
++	mtd->erasesize = (devinfo.blocksize<<10);
++	mtd->oobsize = devinfo.sparesize;
++
++	nand_chip->chipsize = (devinfo.totalsize<<20);
++	nand_chip->page_shift = ffs(mtd->writesize) - 1;
++	nand_chip->pagemask = (nand_chip->chipsize >> nand_chip->page_shift) - 1;
++	nand_chip->phys_erase_shift = ffs(mtd->erasesize) - 1;
++	nand_chip->chip_shift = ffs(nand_chip->chipsize) - 1;//0x1C;//ffs(nand_chip->chipsize) - 1;
++	nand_chip->oob_poi = nand_chip->buffers->databuf + mtd->writesize;
++	nand_chip->badblockpos = 0;
++
++	if (devinfo.pagesize == 4096)
++		nand_chip->ecc.layout = &nand_oob_128;
++	else if (devinfo.pagesize == 2048)
++		nand_chip->ecc.layout = &nand_oob_64;
++	else if (devinfo.pagesize == 512)
++		nand_chip->ecc.layout = &nand_oob_16;
++
++	nand_chip->ecc.layout->eccbytes = devinfo.sparesize-OOB_AVAI_PER_SECTOR*(devinfo.pagesize/NAND_SECTOR_SIZE);
++	for (i = 0; i < nand_chip->ecc.layout->eccbytes; i++)
++		nand_chip->ecc.layout->eccpos[i]=OOB_AVAI_PER_SECTOR*(devinfo.pagesize/NAND_SECTOR_SIZE)+i;
++
++	MSG(INIT, "Support this Device in MTK table! %x \r\n", id);
++	hw->nfi_bus_width = devinfo.iowidth;
++	DRV_WriteReg32(NFI_ACCCON_REG32, devinfo.timmingsetting);
++
++	/* 16-bit bus width */
++	if (hw->nfi_bus_width == 16) {
++		MSG(INIT, "%s : Set the 16-bit I/O settings!\n", MODULE_NAME);
++		nand_chip->options |= NAND_BUSWIDTH_16;
++	}
++	mtd->oobsize = devinfo.sparesize;
++	hw->nfi_cs_num = 1;
++
++	/* Scan to find existance of the device */
++	if (nand_scan(mtd, hw->nfi_cs_num)) {
++		MSG(INIT, "%s : nand_scan fail.\n", MODULE_NAME);
++		err = -ENXIO;
++		goto out;
++	}
++
++	g_page_size = mtd->writesize;
++	platform_set_drvdata(pdev, host);
++	if (hw->nfi_bus_width == 16) {
++		NFI_SET_REG16(NFI_PAGEFMT_REG16, PAGEFMT_DBYTE_EN);
++	}
++
++	nand_chip->select_chip(mtd, 0);
++#if defined(MTK_NAND_BMT)  
++	nand_chip->chipsize -= (BMT_POOL_SIZE) << nand_chip->phys_erase_shift;
++#endif
++	mtd->size = nand_chip->chipsize;
++
++	CFG_BLOCKSIZE = mtd->erasesize;
++
++#if defined(MTK_NAND_BMT)
++	if (!g_bmt) {
++		if (!(g_bmt = init_bmt(nand_chip, BMT_POOL_SIZE))) {
++			MSG(INIT, "Error: init bmt failed\n");
++			return 0;
++		}
++	}
++#endif
++
++	ppdata.of_node = pdev->dev.of_node;
++	err = mtd_device_parse_register(mtd, probe_types, &ppdata,
++					NULL, 0);
++	if (!err) {
++		MSG(INIT, "[mtk_nand] probe successfully!\n");
++		nand_disable_clock();
++		shift_on_bbt = 1;
++		if (load_fact_bbt(mtd) == 0) {
++			int i;
++			for (i = 0; i < 0x100; i++)
++				nand_chip->bbt[i] |= fact_bbt[i];
++		}
++
++		return err;
++	}
++
++out:
++	MSG(INIT, "[NFI] mtk_nand_probe fail, err = %d!\n", err);
++	nand_release(mtd);
++	platform_set_drvdata(pdev, NULL);
++	kfree(host);
++	nand_disable_clock();
++	return err;
++}
++
++static int
++mtk_nand_remove(struct platform_device *pdev)
++{
++	struct mtk_nand_host *host = platform_get_drvdata(pdev);
++	struct mtd_info *mtd = &host->mtd;
++
++	nand_release(mtd);
++	kfree(host);
++	nand_disable_clock();
++
++	return 0;
++}
++
++static const struct of_device_id mt7621_nand_match[] = {
++	{ .compatible = "mtk,mt7621-nand" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, mt7621_nand_match);
++
++static struct platform_driver mtk_nand_driver = {
++	.probe = mtk_nand_probe,
++	.remove = mtk_nand_remove,
++	.driver = {
++		.name = "MT7621-NAND",
++		.owner = THIS_MODULE,
++		.of_match_table = mt7621_nand_match,
++	},
++};
++
++static int __init
++mtk_nand_init(void)
++{
++	printk("MediaTek Nand driver init, version %s\n", VERSION);
++
++	return platform_driver_register(&mtk_nand_driver);
++}
++
++static void __exit
++mtk_nand_exit(void)
++{
++	platform_driver_unregister(&mtk_nand_driver);
++}
++
++module_init(mtk_nand_init);
++module_exit(mtk_nand_exit);
++MODULE_LICENSE("GPL");
+diff --git a/drivers/mtd/nand/mtk_nand.h b/drivers/mtd/nand/mtk_nand.h
+new file mode 100644
+index 0000000..6db88c4
+--- /dev/null
++++ b/drivers/mtd/nand/mtk_nand.h
+@@ -0,0 +1,452 @@
++#ifndef __MTK_NAND_H
++#define __MTK_NAND_H
++
++#define RALINK_NAND_CTRL_BASE         0xBE003000
++#define RALINK_SYSCTL_BASE            0xBE000000
++#define RALINK_NANDECC_CTRL_BASE      0xBE003800
++/*******************************************************************************
++ * NFI Register Definition 
++ *******************************************************************************/
++
++#define NFI_CNFG_REG16  	((volatile P_U16)(NFI_BASE+0x0000))
++#define NFI_PAGEFMT_REG16   ((volatile P_U16)(NFI_BASE+0x0004))
++#define NFI_CON_REG16      	((volatile P_U16)(NFI_BASE+0x0008))
++#define NFI_ACCCON_REG32   	((volatile P_U32)(NFI_BASE+0x000C))
++#define NFI_INTR_EN_REG16   ((volatile P_U16)(NFI_BASE+0x0010))
++#define NFI_INTR_REG16      ((volatile P_U16)(NFI_BASE+0x0014))
++
++#define NFI_CMD_REG16   	((volatile P_U16)(NFI_BASE+0x0020))
++
++#define NFI_ADDRNOB_REG16   ((volatile P_U16)(NFI_BASE+0x0030))
++#define NFI_COLADDR_REG32  	((volatile P_U32)(NFI_BASE+0x0034))
++#define NFI_ROWADDR_REG32  	((volatile P_U32)(NFI_BASE+0x0038))
++
++#define NFI_STRDATA_REG16   ((volatile P_U16)(NFI_BASE+0x0040))
++
++#define NFI_DATAW_REG32    	((volatile P_U32)(NFI_BASE+0x0050))
++#define NFI_DATAR_REG32    	((volatile P_U32)(NFI_BASE+0x0054))
++#define NFI_PIO_DIRDY_REG16 ((volatile P_U16)(NFI_BASE+0x0058))
++
++#define NFI_STA_REG32      	((volatile P_U32)(NFI_BASE+0x0060))
++#define NFI_FIFOSTA_REG16   ((volatile P_U16)(NFI_BASE+0x0064))
++#define NFI_LOCKSTA_REG16   ((volatile P_U16)(NFI_BASE+0x0068))
++
++#define NFI_ADDRCNTR_REG16  ((volatile P_U16)(NFI_BASE+0x0070))
++
++#define NFI_STRADDR_REG32  	((volatile P_U32)(NFI_BASE+0x0080))
++#define NFI_BYTELEN_REG16   ((volatile P_U16)(NFI_BASE+0x0084))
++
++#define NFI_CSEL_REG16      ((volatile P_U16)(NFI_BASE+0x0090))
++#define NFI_IOCON_REG16     ((volatile P_U16)(NFI_BASE+0x0094))
++
++#define NFI_FDM0L_REG32    	((volatile P_U32)(NFI_BASE+0x00A0))
++#define NFI_FDM0M_REG32    	((volatile P_U32)(NFI_BASE+0x00A4))
++
++#define NFI_LOCK_REG16	  	((volatile P_U16)(NFI_BASE+0x0100))
++#define NFI_LOCKCON_REG32  	((volatile P_U32)(NFI_BASE+0x0104))
++#define NFI_LOCKANOB_REG16  ((volatile P_U16)(NFI_BASE+0x0108))
++#define NFI_LOCK00ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0110))
++#define NFI_LOCK00FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0114))
++#define NFI_LOCK01ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0118))
++#define NFI_LOCK01FMT_REG32 ((volatile P_U32)(NFI_BASE+0x011C))
++#define NFI_LOCK02ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0120))
++#define NFI_LOCK02FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0124))
++#define NFI_LOCK03ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0128))
++#define NFI_LOCK03FMT_REG32 ((volatile P_U32)(NFI_BASE+0x012C))
++#define NFI_LOCK04ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0130))
++#define NFI_LOCK04FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0134))
++#define NFI_LOCK05ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0138))
++#define NFI_LOCK05FMT_REG32 ((volatile P_U32)(NFI_BASE+0x013C))
++#define NFI_LOCK06ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0140))
++#define NFI_LOCK06FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0144))
++#define NFI_LOCK07ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0148))
++#define NFI_LOCK07FMT_REG32 ((volatile P_U32)(NFI_BASE+0x014C))
++#define NFI_LOCK08ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0150))
++#define NFI_LOCK08FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0154))
++#define NFI_LOCK09ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0158))
++#define NFI_LOCK09FMT_REG32 ((volatile P_U32)(NFI_BASE+0x015C))
++#define NFI_LOCK10ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0160))
++#define NFI_LOCK10FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0164))
++#define NFI_LOCK11ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0168))
++#define NFI_LOCK11FMT_REG32 ((volatile P_U32)(NFI_BASE+0x016C))
++#define NFI_LOCK12ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0170))
++#define NFI_LOCK12FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0174))
++#define NFI_LOCK13ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0178))
++#define NFI_LOCK13FMT_REG32 ((volatile P_U32)(NFI_BASE+0x017C))
++#define NFI_LOCK14ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0180))
++#define NFI_LOCK14FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0184))
++#define NFI_LOCK15ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0188))
++#define NFI_LOCK15FMT_REG32 ((volatile P_U32)(NFI_BASE+0x018C))
++
++#define NFI_FIFODATA0_REG32 ((volatile P_U32)(NFI_BASE+0x0190))
++#define NFI_FIFODATA1_REG32 ((volatile P_U32)(NFI_BASE+0x0194))
++#define NFI_FIFODATA2_REG32 ((volatile P_U32)(NFI_BASE+0x0198))
++#define NFI_FIFODATA3_REG32 ((volatile P_U32)(NFI_BASE+0x019C))
++#define NFI_MASTERSTA_REG16 ((volatile P_U16)(NFI_BASE+0x0210))
++
++
++/*******************************************************************************
++ * NFI Register Field Definition 
++ *******************************************************************************/
++
++/* NFI_CNFG */
++#define CNFG_AHB             (0x0001)
++#define CNFG_READ_EN         (0x0002)
++#define CNFG_DMA_BURST_EN    (0x0004)
++#define CNFG_BYTE_RW         (0x0040)
++#define CNFG_HW_ECC_EN       (0x0100)
++#define CNFG_AUTO_FMT_EN     (0x0200)
++#define CNFG_OP_IDLE         (0x0000)
++#define CNFG_OP_READ         (0x1000)
++#define CNFG_OP_SRD          (0x2000)
++#define CNFG_OP_PRGM         (0x3000)
++#define CNFG_OP_ERASE        (0x4000)
++#define CNFG_OP_RESET        (0x5000)
++#define CNFG_OP_CUST         (0x6000)
++#define CNFG_OP_MODE_MASK    (0x7000)
++#define CNFG_OP_MODE_SHIFT   (12)
++
++/* NFI_PAGEFMT */
++#define PAGEFMT_512          (0x0000)
++#define PAGEFMT_2K           (0x0001)
++#define PAGEFMT_4K           (0x0002)
++
++#define PAGEFMT_PAGE_MASK    (0x0003)
++
++#define PAGEFMT_DBYTE_EN     (0x0008)
++
++#define PAGEFMT_SPARE_16     (0x0000)
++#define PAGEFMT_SPARE_26     (0x0001)
++#define PAGEFMT_SPARE_27     (0x0002)
++#define PAGEFMT_SPARE_28     (0x0003)
++#define PAGEFMT_SPARE_MASK   (0x0030)
++#define PAGEFMT_SPARE_SHIFT  (4)
++
++#define PAGEFMT_FDM_MASK     (0x0F00)
++#define PAGEFMT_FDM_SHIFT    (8)
++
++#define PAGEFMT_FDM_ECC_MASK  (0xF000)
++#define PAGEFMT_FDM_ECC_SHIFT (12)
++
++/* NFI_CON */
++#define CON_FIFO_FLUSH       (0x0001)
++#define CON_NFI_RST          (0x0002)
++#define CON_NFI_SRD          (0x0010)
++
++#define CON_NFI_NOB_MASK     (0x0060)
++#define CON_NFI_NOB_SHIFT    (5)
++
++#define CON_NFI_BRD          (0x0100)
++#define CON_NFI_BWR          (0x0200)
++
++#define CON_NFI_SEC_MASK     (0xF000)
++#define CON_NFI_SEC_SHIFT    (12)
++
++/* NFI_ACCCON */
++#define ACCCON_SETTING       ()
++
++/* NFI_INTR_EN */
++#define INTR_RD_DONE_EN      (0x0001)
++#define INTR_WR_DONE_EN      (0x0002)
++#define INTR_RST_DONE_EN     (0x0004)
++#define INTR_ERASE_DONE_EN   (0x0008)
++#define INTR_BSY_RTN_EN      (0x0010)
++#define INTR_ACC_LOCK_EN     (0x0020)
++#define INTR_AHB_DONE_EN     (0x0040)
++#define INTR_ALL_INTR_DE     (0x0000)
++#define INTR_ALL_INTR_EN     (0x007F)
++
++/* NFI_INTR */
++#define INTR_RD_DONE         (0x0001)
++#define INTR_WR_DONE         (0x0002)
++#define INTR_RST_DONE        (0x0004)
++#define INTR_ERASE_DONE      (0x0008)
++#define INTR_BSY_RTN         (0x0010)
++#define INTR_ACC_LOCK        (0x0020)
++#define INTR_AHB_DONE        (0x0040)
++
++/* NFI_ADDRNOB */
++#define ADDR_COL_NOB_MASK    (0x0003)
++#define ADDR_COL_NOB_SHIFT   (0)
++#define ADDR_ROW_NOB_MASK    (0x0030)
++#define ADDR_ROW_NOB_SHIFT   (4)
++
++/* NFI_STA */
++#define STA_READ_EMPTY       (0x00001000)
++#define STA_ACC_LOCK         (0x00000010)
++#define STA_CMD_STATE        (0x00000001)
++#define STA_ADDR_STATE       (0x00000002)
++#define STA_DATAR_STATE      (0x00000004)
++#define STA_DATAW_STATE      (0x00000008)
++
++#define STA_NAND_FSM_MASK    (0x1F000000)
++#define STA_NAND_BUSY        (0x00000100)
++#define STA_NAND_BUSY_RETURN (0x00000200)
++#define STA_NFI_FSM_MASK     (0x000F0000)
++#define STA_NFI_OP_MASK      (0x0000000F)
++
++/* NFI_FIFOSTA */
++#define FIFO_RD_EMPTY        (0x0040)
++#define FIFO_RD_FULL         (0x0080)
++#define FIFO_WR_FULL         (0x8000)
++#define FIFO_WR_EMPTY        (0x4000)
++#define FIFO_RD_REMAIN(x)    (0x1F&(x))
++#define FIFO_WR_REMAIN(x)    ((0x1F00&(x))>>8)
++
++/* NFI_ADDRCNTR */
++#define ADDRCNTR_CNTR(x)     ((0xF000&(x))>>12)
++#define ADDRCNTR_OFFSET(x)   (0x03FF&(x))
++
++/* NFI_LOCK */
++#define NFI_LOCK_ON          (0x0001)
++
++/* NFI_LOCKANOB */
++#define PROG_RADD_NOB_MASK   (0x7000)
++#define PROG_RADD_NOB_SHIFT  (12)
++#define PROG_CADD_NOB_MASK   (0x0300)
++#define PROG_CADD_NOB_SHIFT  (8)
++#define ERASE_RADD_NOB_MASK   (0x0070)
++#define ERASE_RADD_NOB_SHIFT  (4)
++#define ERASE_CADD_NOB_MASK   (0x0007)
++#define ERASE_CADD_NOB_SHIFT  (0)
++
++/*******************************************************************************
++ * ECC Register Definition 
++ *******************************************************************************/
++
++#define ECC_ENCCON_REG16	((volatile P_U16)(NFIECC_BASE+0x0000))
++#define ECC_ENCCNFG_REG32  	((volatile P_U32)(NFIECC_BASE+0x0004))
++#define ECC_ENCDIADDR_REG32	((volatile P_U32)(NFIECC_BASE+0x0008))
++#define ECC_ENCIDLE_REG32  	((volatile P_U32)(NFIECC_BASE+0x000C))
++#define ECC_ENCPAR0_REG32   ((volatile P_U32)(NFIECC_BASE+0x0010))
++#define ECC_ENCPAR1_REG32   ((volatile P_U32)(NFIECC_BASE+0x0014))
++#define ECC_ENCPAR2_REG32   ((volatile P_U32)(NFIECC_BASE+0x0018))
++#define ECC_ENCPAR3_REG32   ((volatile P_U32)(NFIECC_BASE+0x001C))
++#define ECC_ENCPAR4_REG32   ((volatile P_U32)(NFIECC_BASE+0x0020))
++#define ECC_ENCSTA_REG32    ((volatile P_U32)(NFIECC_BASE+0x0024))
++#define ECC_ENCIRQEN_REG16  ((volatile P_U16)(NFIECC_BASE+0x0028))
++#define ECC_ENCIRQSTA_REG16 ((volatile P_U16)(NFIECC_BASE+0x002C))
++
++#define ECC_DECCON_REG16    ((volatile P_U16)(NFIECC_BASE+0x0100))
++#define ECC_DECCNFG_REG32   ((volatile P_U32)(NFIECC_BASE+0x0104))
++#define ECC_DECDIADDR_REG32 ((volatile P_U32)(NFIECC_BASE+0x0108))
++#define ECC_DECIDLE_REG16   ((volatile P_U16)(NFIECC_BASE+0x010C))
++#define ECC_DECFER_REG16    ((volatile P_U16)(NFIECC_BASE+0x0110))
++#define ECC_DECENUM_REG32   ((volatile P_U32)(NFIECC_BASE+0x0114))
++#define ECC_DECDONE_REG16   ((volatile P_U16)(NFIECC_BASE+0x0118))
++#define ECC_DECEL0_REG32    ((volatile P_U32)(NFIECC_BASE+0x011C))
++#define ECC_DECEL1_REG32    ((volatile P_U32)(NFIECC_BASE+0x0120))
++#define ECC_DECEL2_REG32    ((volatile P_U32)(NFIECC_BASE+0x0124))
++#define ECC_DECEL3_REG32    ((volatile P_U32)(NFIECC_BASE+0x0128))
++#define ECC_DECEL4_REG32    ((volatile P_U32)(NFIECC_BASE+0x012C))
++#define ECC_DECEL5_REG32    ((volatile P_U32)(NFIECC_BASE+0x0130))
++#define ECC_DECIRQEN_REG16  ((volatile P_U16)(NFIECC_BASE+0x0134))
++#define ECC_DECIRQSTA_REG16 ((volatile P_U16)(NFIECC_BASE+0x0138))
++#define ECC_FDMADDR_REG32   ((volatile P_U32)(NFIECC_BASE+0x013C))
++#define ECC_DECFSM_REG32    ((volatile P_U32)(NFIECC_BASE+0x0140))
++#define ECC_SYNSTA_REG32    ((volatile P_U32)(NFIECC_BASE+0x0144))
++#define ECC_DECNFIDI_REG32  ((volatile P_U32)(NFIECC_BASE+0x0148))
++#define ECC_SYN0_REG32      ((volatile P_U32)(NFIECC_BASE+0x014C))
++
++/*******************************************************************************
++ * ECC register definition
++ *******************************************************************************/
++/* ECC_ENCON */
++#define ENC_EN             		(0x0001)
++#define ENC_DE                 	(0x0000)
++
++/* ECC_ENCCNFG */
++#define ECC_CNFG_ECC4          	(0x0000)
++#define ECC_CNFG_ECC6          	(0x0001)
++#define ECC_CNFG_ECC8          	(0x0002)
++#define ECC_CNFG_ECC10         	(0x0003)
++#define ECC_CNFG_ECC12         	(0x0004)
++#define ECC_CNFG_ECC_MASK      	(0x00000007)
++
++#define ENC_CNFG_NFI           	(0x0010)
++#define ENC_CNFG_MODE_MASK     	(0x0010)
++
++#define ENC_CNFG_META6         	(0x10300000)
++#define ENC_CNFG_META8         	(0x10400000)
++
++#define ENC_CNFG_MSG_MASK  		(0x1FFF0000)
++#define ENC_CNFG_MSG_SHIFT 		(0x10)
++
++/* ECC_ENCIDLE */
++#define ENC_IDLE           		(0x0001)
++
++/* ECC_ENCSTA */
++#define STA_FSM            		(0x001F)
++#define STA_COUNT_PS       		(0xFF10)
++#define STA_COUNT_MS       		(0x3FFF0000)
++
++/* ECC_ENCIRQEN */
++#define ENC_IRQEN          		(0x0001)
++
++/* ECC_ENCIRQSTA */
++#define ENC_IRQSTA         		(0x0001)
++
++/* ECC_DECCON */
++#define DEC_EN             		(0x0001)
++#define DEC_DE             		(0x0000)
++
++/* ECC_ENCCNFG */
++#define DEC_CNFG_ECC4          (0x0000)
++//#define DEC_CNFG_ECC6          (0x0001)
++//#define DEC_CNFG_ECC12         (0x0002)
++#define DEC_CNFG_NFI           (0x0010)
++//#define DEC_CNFG_META6         (0x10300000)
++//#define DEC_CNFG_META8         (0x10400000)
++
++#define DEC_CNFG_FER           (0x01000)
++#define DEC_CNFG_EL            (0x02000)
++#define DEC_CNFG_CORRECT       (0x03000)
++#define DEC_CNFG_TYPE_MASK     (0x03000)
++
++#define DEC_CNFG_EMPTY_EN      (0x80000000)
++
++#define DEC_CNFG_CODE_MASK     (0x1FFF0000)
++#define DEC_CNFG_CODE_SHIFT    (0x10)
++
++/* ECC_DECIDLE */
++#define DEC_IDLE           		(0x0001)
++
++/* ECC_DECFER */
++#define DEC_FER0               (0x0001)
++#define DEC_FER1               (0x0002)
++#define DEC_FER2               (0x0004)
++#define DEC_FER3               (0x0008)
++#define DEC_FER4               (0x0010)
++#define DEC_FER5               (0x0020)
++#define DEC_FER6               (0x0040)
++#define DEC_FER7               (0x0080)
++
++/* ECC_DECENUM */
++#define ERR_NUM0               (0x0000000F)
++#define ERR_NUM1               (0x000000F0)
++#define ERR_NUM2               (0x00000F00)
++#define ERR_NUM3               (0x0000F000)
++#define ERR_NUM4               (0x000F0000)
++#define ERR_NUM5               (0x00F00000)
++#define ERR_NUM6               (0x0F000000)
++#define ERR_NUM7               (0xF0000000)
++
++/* ECC_DECDONE */
++#define DEC_DONE0               (0x0001)
++#define DEC_DONE1               (0x0002)
++#define DEC_DONE2               (0x0004)
++#define DEC_DONE3               (0x0008)
++#define DEC_DONE4               (0x0010)
++#define DEC_DONE5               (0x0020)
++#define DEC_DONE6               (0x0040)
++#define DEC_DONE7               (0x0080)
++
++/* ECC_DECIRQEN */
++#define DEC_IRQEN         		(0x0001)
++
++/* ECC_DECIRQSTA */
++#define DEC_IRQSTA      		(0x0001)
++
++#define CHIPVER_ECO_1           (0x8a00)
++#define CHIPVER_ECO_2           (0x8a01)
++
++//#define NAND_PFM
++
++/*******************************************************************************
++ * Data Structure Definition
++ *******************************************************************************/
++struct mtk_nand_host 
++{
++	struct nand_chip		nand_chip;
++	struct mtd_info			mtd;
++	struct mtk_nand_host_hw	*hw;
++};
++
++struct NAND_CMD
++{
++	u32	u4ColAddr;
++	u32 u4RowAddr;
++	u32 u4OOBRowAddr;
++	u8	au1OOB[288];
++	u8*	pDataBuf;
++#ifdef NAND_PFM	
++	u32 pureReadOOB;
++	u32 pureReadOOBNum;
++#endif
++};
++
++/*
++ *	ECC layout control structure. Exported to userspace for
++ *  diagnosis and to allow creation of raw images
++struct nand_ecclayout {
++	uint32_t eccbytes;
++	uint32_t eccpos[64];
++	uint32_t oobavail;
++	struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
++};
++*/
++#define __DEBUG_NAND		1			/* Debug information on/off */
++
++/* Debug message event */
++#define DBG_EVT_NONE		0x00000000	/* No event */
++#define DBG_EVT_INIT		0x00000001	/* Initial related event */
++#define DBG_EVT_VERIFY		0x00000002	/* Verify buffer related event */
++#define DBG_EVT_PERFORMANCE	0x00000004	/* Performance related event */
++#define DBG_EVT_READ		0x00000008	/* Read related event */
++#define DBG_EVT_WRITE		0x00000010	/* Write related event */
++#define DBG_EVT_ERASE		0x00000020	/* Erase related event */
++#define DBG_EVT_BADBLOCK	0x00000040	/* Badblock related event */
++#define DBG_EVT_POWERCTL	0x00000080	/* Suspend/Resume related event */
++
++#define DBG_EVT_ALL			0xffffffff
++
++#define DBG_EVT_MASK      	(DBG_EVT_INIT)
++
++#if __DEBUG_NAND
++#define MSG(evt, fmt, args...) \
++do {	\
++	if ((DBG_EVT_##evt) & DBG_EVT_MASK) { \
++		printk(fmt, ##args); \
++	} \
++} while(0)
++
++#define MSG_FUNC_ENTRY(f)	MSG(FUC, "<FUN_ENT>: %s\n", __FUNCTION__)
++#else
++#define MSG(evt, fmt, args...) do{}while(0)
++#define MSG_FUNC_ENTRY(f)	   do{}while(0)
++#endif
++
++#define RAMDOM_READ 1<<0
++#define CACHE_READ  1<<1
++
++typedef struct
++{
++   u16 id;          //deviceid+menuid
++   u32 ext_id; 
++   u8  addr_cycle;
++   u8  iowidth;
++   u16 totalsize;   
++   u16 blocksize;
++   u16 pagesize;
++   u16 sparesize;
++   u32 timmingsetting;
++   char devciename[14];
++   u32 advancedmode;   //
++}flashdev_info,*pflashdev_info;
++
++/* NAND driver */
++#if 0
++struct mtk_nand_host_hw {
++    unsigned int nfi_bus_width;		    /* NFI_BUS_WIDTH */ 
++	unsigned int nfi_access_timing;		/* NFI_ACCESS_TIMING */  
++	unsigned int nfi_cs_num;			/* NFI_CS_NUM */
++	unsigned int nand_sec_size;			/* NAND_SECTOR_SIZE */
++	unsigned int nand_sec_shift;		/* NAND_SECTOR_SHIFT */
++	unsigned int nand_ecc_size;
++	unsigned int nand_ecc_bytes;
++	unsigned int nand_ecc_mode;
++};
++extern struct mtk_nand_host_hw mt7621_nand_hw;
++extern u32	CFG_BLOCKSIZE;
++#endif
++#endif
+diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
+index d340b2f..d83655f 100644
+--- a/drivers/mtd/nand/nand_base.c
++++ b/drivers/mtd/nand/nand_base.c
+@@ -90,7 +90,7 @@ static struct nand_ecclayout nand_oob_128 = {
+ 		 .length = 78} }
+ };
+ 
+-static int nand_get_device(struct mtd_info *mtd, int new_state);
++int nand_get_device(struct mtd_info *mtd, int new_state);
+ 
+ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
+ 			     struct mtd_oob_ops *ops);
+@@ -128,7 +128,7 @@ static int check_offs_len(struct mtd_info *mtd,
+  *
+  * Release chip lock and wake up anyone waiting on the device.
+  */
+-static void nand_release_device(struct mtd_info *mtd)
++void nand_release_device(struct mtd_info *mtd)
+ {
+ 	struct nand_chip *chip = mtd->priv;
+ 
+@@ -736,7 +736,7 @@ static void panic_nand_get_device(struct nand_chip *chip,
+  *
+  * Get the device and lock it for exclusive access
+  */
+-static int
++int
+ nand_get_device(struct mtd_info *mtd, int new_state)
+ {
+ 	struct nand_chip *chip = mtd->priv;
+diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
+index bc06196..da93baf 100644
+--- a/drivers/mtd/nand/nand_bbt.c
++++ b/drivers/mtd/nand/nand_bbt.c
+@@ -1391,5 +1391,24 @@ int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs)
+ 	return ret;
+ }
+ 
++void nand_bbt_set(struct mtd_info *mtd, int page, int flag)
++{
++	struct nand_chip *this = mtd->priv;
++	int block;
++
++	block = (int)(page >> (this->bbt_erase_shift - this->page_shift - 1));
++	this->bbt[block >> 3] &= ~(0x03 << (block & 0x6));
++	this->bbt[block >> 3] |= (flag & 0x3) << (block & 0x6);
++}
++
++int nand_bbt_get(struct mtd_info *mtd, int page)
++{
++	struct nand_chip *this = mtd->priv;
++	int block;
++
++	block = (int)(page >> (this->bbt_erase_shift - this->page_shift - 1));
++	return (this->bbt[block >> 3] >> (block & 0x06)) & 0x03;
++}
++
+ EXPORT_SYMBOL(nand_scan_bbt);
+ EXPORT_SYMBOL(nand_default_bbt);
+diff --git a/drivers/mtd/nand/nand_def.h b/drivers/mtd/nand/nand_def.h
+new file mode 100644
+index 0000000..82e957d
+--- /dev/null
++++ b/drivers/mtd/nand/nand_def.h
+@@ -0,0 +1,123 @@
++#ifndef __NAND_DEF_H__
++#define __NAND_DEF_H__
++
++#define VERSION  	"v2.1 Fix AHB virt2phys error"
++#define MODULE_NAME	"# MTK NAND #"
++#define PROCNAME    "driver/nand"
++
++#undef TESTTIME
++//#define __UBOOT_NAND__			1
++#define __KERNEL_NAND__		1
++//#define __PRELOADER_NAND__	1
++//#define PMT 1
++//#define _MTK_NAND_DUMMY_DRIVER
++//#define CONFIG_BADBLOCK_CHECK	1
++//#ifdef CONFIG_BADBLOCK_CHECK
++//#define MTK_NAND_BMT	1
++//#endif
++#define ECC_ENABLE		1
++#define MANUAL_CORRECT	1
++//#define __INTERNAL_USE_AHB_MODE__ 	(0)
++#define SKIP_BAD_BLOCK
++#define FACT_BBT
++
++#ifndef NAND_OTP_SUPPORT
++#define NAND_OTP_SUPPORT 0
++#endif
++
++/*******************************************************************************
++ * Macro definition 
++ *******************************************************************************/
++//#define NFI_SET_REG32(reg, value)   (DRV_WriteReg32(reg, DRV_Reg32(reg) | (value))) 
++//#define NFI_SET_REG16(reg, value)   (DRV_WriteReg16(reg, DRV_Reg16(reg) | (value)))
++//#define NFI_CLN_REG32(reg, value)   (DRV_WriteReg32(reg, DRV_Reg32(reg) & (~(value))))
++//#define NFI_CLN_REG16(reg, value)   (DRV_WriteReg16(reg, DRV_Reg16(reg) & (~(value))))
++
++#if defined (__KERNEL_NAND__)
++#define NFI_SET_REG32(reg, value) \
++do {	\
++	g_value = (DRV_Reg32(reg) | (value));\
++	DRV_WriteReg32(reg, g_value); \
++} while(0)
++
++#define NFI_SET_REG16(reg, value) \
++do {	\
++	g_value = (DRV_Reg16(reg) | (value));\
++	DRV_WriteReg16(reg, g_value); \
++} while(0)
++
++#define NFI_CLN_REG32(reg, value) \
++do {	\
++	g_value = (DRV_Reg32(reg) & (~(value)));\
++	DRV_WriteReg32(reg, g_value); \
++} while(0)
++
++#define NFI_CLN_REG16(reg, value) \
++do {	\
++	g_value = (DRV_Reg16(reg) & (~(value)));\
++	DRV_WriteReg16(reg, g_value); \
++} while(0)
++#endif
++
++#define NFI_WAIT_STATE_DONE(state) do{;}while (__raw_readl(NFI_STA_REG32) & state)
++#define NFI_WAIT_TO_READY()  do{;}while (!(__raw_readl(NFI_STA_REG32) & STA_BUSY2READY))
++
++
++#define NAND_SECTOR_SIZE (512)
++#define OOB_PER_SECTOR      (16)
++#define OOB_AVAI_PER_SECTOR (8)
++
++#ifndef PART_SIZE_BMTPOOL
++#define BMT_POOL_SIZE       (80)
++#else
++#define BMT_POOL_SIZE (PART_SIZE_BMTPOOL)
++#endif
++
++#define PMT_POOL_SIZE	(2)
++
++#define TIMEOUT_1   0x1fff
++#define TIMEOUT_2   0x8ff
++#define TIMEOUT_3   0xffff
++#define TIMEOUT_4   0xffff//5000   //PIO
++
++
++/* temporarity definiation */
++#if !defined (__KERNEL_NAND__) 
++#define KERN_INFO
++#define KERN_WARNING
++#define KERN_ERR
++#define PAGE_SIZE	(4096)
++#endif
++#define AddStorageTrace				//AddStorageTrace
++#define STORAGE_LOGGER_MSG_NAND		0
++#define NFI_BASE 					RALINK_NAND_CTRL_BASE
++#define NFIECC_BASE 				RALINK_NANDECC_CTRL_BASE
++
++#ifdef __INTERNAL_USE_AHB_MODE__
++#define MT65xx_POLARITY_LOW   0
++#define MT65XX_PDN_PERI_NFI   0
++#define MT65xx_EDGE_SENSITIVE 0
++#define MT6575_NFI_IRQ_ID                    (58)
++#endif
++
++#if defined (__KERNEL_NAND__)
++#define RALINK_REG(x)		(*((volatile u32 *)(x)))	
++#define __virt_to_phys(x)	virt_to_phys((volatile void*)x)
++#else
++#define CONFIG_MTD_NAND_VERIFY_WRITE	(1)
++#define printk	printf
++#define ra_dbg printf
++#define BUG()							//BUG()
++#define BUG_ON(x)						//BUG_ON()
++#define NUM_PARTITIONS 				1
++#endif
++
++#define NFI_DEFAULT_ACCESS_TIMING        (0x30C77fff)	//(0x44333)
++
++//uboot only support 1 cs
++#define NFI_CS_NUM                  (1)
++#define NFI_DEFAULT_CS              (0)
++
++#include "mt6575_typedefs.h"
++
++#endif /* __NAND_DEF_H__ */
+diff --git a/drivers/mtd/nand/nand_device_list.h b/drivers/mtd/nand/nand_device_list.h
+new file mode 100644
+index 0000000..4c36b3a
+--- /dev/null
++++ b/drivers/mtd/nand/nand_device_list.h
+@@ -0,0 +1,55 @@
++/* Copyright Statement:
++ *
++ * This software/firmware and related documentation ("MediaTek Software") are
++ * protected under relevant copyright laws. The information contained herein
++ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
++ * Without the prior written permission of MediaTek inc. and/or its licensors,
++ * any reproduction, modification, use or disclosure of MediaTek Software,
++ * and information contained herein, in whole or in part, shall be strictly prohibited.
++ */
++/* MediaTek Inc. (C) 2010. All rights reserved.
++ *
++ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
++ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
++ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
++ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
++ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
++ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
++ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
++ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
++ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++ *
++ * The following software/firmware and/or related documentation ("MediaTek Software")
++ * have been modified by MediaTek Inc. All revisions are subject to any receiver's
++ * applicable license agreements with MediaTek Inc.
++ */
++
++#ifndef __NAND_DEVICE_LIST_H__
++#define __NAND_DEVICE_LIST_H__
++
++static const flashdev_info gen_FlashTable[]={
++	{0x20BC, 0x105554, 5, 16, 512, 128, 2048, 64, 0x1123, "EHD013151MA_5", 0},
++	{0xECBC, 0x005554, 5, 16, 512, 128, 2048, 64, 0x1123, "K524G2GACB_A0", 0},
++	{0x2CBC, 0x905556, 5, 16, 512, 128, 2048, 64, 0x21044333, "MT29C4G96MAZA", 0},
++	{0xADBC, 0x905554, 5, 16, 512, 128, 2048, 64, 0x10801011, "H9DA4GH4JJAMC", 0},
++    {0x01F1, 0x801D01, 4, 8, 128, 128, 2048, 64, 0x30C77fff, "S34ML01G100TF", 0},
++    {0x92F1, 0x8095FF, 4, 8, 128, 128, 2048, 64, 0x30C77fff, "F59L1G81A", 0},
++	{0xECD3, 0x519558, 5, 8, 1024, 128, 2048, 64, 0x44333, "K9K8G8000", 0},
++    {0xC2F1, 0x801DC2, 4, 8, 128, 128, 2048, 64, 0x30C77fff, "MX30LF1G08AA", 0},
++    {0x98D3, 0x902676, 5, 8, 1024, 256, 4096, 224, 0x00C25332, "TC58NVG3S0F", 0},
++    {0x01DA, 0x909546, 5, 8, 256, 128, 2048, 128, 0x30C77fff, "S34ML02G200TF", 0},
++    {0x01DC, 0x909556, 5, 8, 512, 128, 2048, 128, 0x30C77fff, "S34ML04G200TF", 0},
++	{0x0000, 0x000000, 0, 0, 0, 0, 0, 0, 0, "xxxxxxxxxx", 0},
++};
++
++
++#endif
+diff --git a/drivers/mtd/nand/partition.h b/drivers/mtd/nand/partition.h
+new file mode 100644
+index 0000000..034e1af
+--- /dev/null
++++ b/drivers/mtd/nand/partition.h
+@@ -0,0 +1,115 @@
++/* Copyright Statement:
++ *
++ * This software/firmware and related documentation ("MediaTek Software") are
++ * protected under relevant copyright laws. The information contained herein
++ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
++ * Without the prior written permission of MediaTek inc. and/or its licensors,
++ * any reproduction, modification, use or disclosure of MediaTek Software,
++ * and information contained herein, in whole or in part, shall be strictly prohibited.
++ */
++/* MediaTek Inc. (C) 2010. All rights reserved.
++ *
++ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
++ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
++ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
++ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
++ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
++ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
++ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
++ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
++ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++ *
++ * The following software/firmware and/or related documentation ("MediaTek Software")
++ * have been modified by MediaTek Inc. All revisions are subject to any receiver's
++ * applicable license agreements with MediaTek Inc.
++ */
++
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/nand.h>
++#include <linux/mtd/partitions.h>
++
++#define RECONFIG_PARTITION_SIZE 1
++
++#define MTD_BOOT_PART_SIZE  0x80000
++#define MTD_CONFIG_PART_SIZE    0x20000
++#define MTD_FACTORY_PART_SIZE   0x20000
++
++extern unsigned int  CFG_BLOCKSIZE;
++#define LARGE_MTD_BOOT_PART_SIZE       (CFG_BLOCKSIZE<<2)
++#define LARGE_MTD_CONFIG_PART_SIZE     (CFG_BLOCKSIZE<<2)
++#define LARGE_MTD_FACTORY_PART_SIZE    (CFG_BLOCKSIZE<<1)
++
++/*=======================================================================*/
++/* NAND PARTITION Mapping                                                  */
++/*=======================================================================*/
++//#ifdef CONFIG_MTD_PARTITIONS
++static struct mtd_partition g_pasStatic_Partition[] = {
++	{
++                name:           "ALL",
++                size:           MTDPART_SIZ_FULL,
++                offset:         0,
++        },
++        /* Put your own partition definitions here */
++        {
++                name:           "Bootloader",
++                size:           MTD_BOOT_PART_SIZE,
++                offset:         0,
++        }, {
++                name:           "Config",
++                size:           MTD_CONFIG_PART_SIZE,
++                offset:         MTDPART_OFS_APPEND
++        }, {
++                name:           "Factory",
++                size:           MTD_FACTORY_PART_SIZE,
++                offset:         MTDPART_OFS_APPEND
++#ifdef CONFIG_RT2880_ROOTFS_IN_FLASH
++        }, {
++                name:           "Kernel",
++                size:           MTD_KERN_PART_SIZE,
++                offset:         MTDPART_OFS_APPEND,
++        }, {
++                name:           "RootFS",
++                size:           MTD_ROOTFS_PART_SIZE,
++                offset:         MTDPART_OFS_APPEND,
++#ifdef CONFIG_ROOTFS_IN_FLASH_NO_PADDING
++        }, {
++                name:           "Kernel_RootFS",
++                size:           MTD_KERN_PART_SIZE + MTD_ROOTFS_PART_SIZE,
++                offset:         MTD_BOOT_PART_SIZE + MTD_CONFIG_PART_SIZE + MTD_FACTORY_PART_SIZE,
++#endif
++#else //CONFIG_RT2880_ROOTFS_IN_RAM
++        }, {
++                name:           "Kernel",
++                size:           0x10000,
++                offset:         MTDPART_OFS_APPEND,
++#endif
++#ifdef CONFIG_DUAL_IMAGE
++        }, {
++                name:           "Kernel2",
++                size:           MTD_KERN2_PART_SIZE,
++                offset:         MTD_KERN2_PART_OFFSET,
++#ifdef CONFIG_RT2880_ROOTFS_IN_FLASH
++        }, {
++                name:           "RootFS2",
++                size:           MTD_ROOTFS2_PART_SIZE,
++                offset:         MTD_ROOTFS2_PART_OFFSET,
++#endif
++#endif
++        }
++
++};
++
++#define NUM_PARTITIONS ARRAY_SIZE(g_pasStatic_Partition)
++extern int part_num;	// = NUM_PARTITIONS;
++//#endif
++#undef RECONFIG_PARTITION_SIZE
++
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/rt305x/config-3.10 b/target/linux/ramips/rt305x/config-3.10
index e1772945d5..fc79dec145 100644
--- a/target/linux/ramips/rt305x/config-3.10
+++ b/target/linux/ramips/rt305x/config-3.10
@@ -142,6 +142,7 @@ CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SOC_MT7620 is not set
+# CONFIG_SOC_MT7621 is not set
 # CONFIG_SOC_RT288X is not set
 CONFIG_SOC_RT305X=y
 # CONFIG_SOC_RT3883 is not set
diff --git a/target/linux/ramips/rt3883/config-3.10 b/target/linux/ramips/rt3883/config-3.10
index 54b23258fd..911d7033b7 100644
--- a/target/linux/ramips/rt3883/config-3.10
+++ b/target/linux/ramips/rt3883/config-3.10
@@ -150,6 +150,7 @@ CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SOC_MT7620 is not set
+# CONFIG_SOC_MT7621 is not set
 # CONFIG_SOC_RT288X is not set
 # CONFIG_SOC_RT305X is not set
 CONFIG_SOC_RT3883=y