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| author | Felix Fietkau <nbd@openwrt.org> | 2015-11-21 10:55:05 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-11-21 10:55:05 +0000 |
| commit | 9c114740efdffc4d06a3b8926b095fb16c65c136 (patch) | |
| tree | a99f6fe1ec54b9cfd5fc315e98416643058bad61 | |
| parent | 49d4a980d76d5601e9fe29941b5c04b6cea08a65 (diff) | |
| download | master-31e0f0ae-9c114740efdffc4d06a3b8926b095fb16c65c136.tar.gz master-31e0f0ae-9c114740efdffc4d06a3b8926b095fb16c65c136.tar.bz2 master-31e0f0ae-9c114740efdffc4d06a3b8926b095fb16c65c136.zip | |
ipq806x: reduce PCIe buffer size setting to fix potential data corruption issues
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 47545
| -rw-r--r-- | target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch | 4 | ||||
| -rw-r--r-- | target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch b/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch index 11c9810fe2..c0b65c712b 100644 --- a/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch +++ b/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch @@ -229,8 +229,8 @@ + writel(upper_32_bits(pp->mem_bus_addr), + pcie->dbi + PCIE20_PLR_IATU_UTAR); + -+ /* 1K PCIE buffer setting */ -+ writel(0x3, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); ++ /* 256B PCIE buffer setting */ ++ writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); + writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); +} + diff --git a/target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch b/target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch index 11c9810fe2..c0b65c712b 100644 --- a/target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch +++ b/target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch @@ -229,8 +229,8 @@ + writel(upper_32_bits(pp->mem_bus_addr), + pcie->dbi + PCIE20_PLR_IATU_UTAR); + -+ /* 1K PCIE buffer setting */ -+ writel(0x3, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); ++ /* 256B PCIE buffer setting */ ++ writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); + writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); +} + |