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authorFelix Fietkau <nbd@openwrt.org>2015-11-02 18:20:51 +0000
committerFelix Fietkau <nbd@openwrt.org>2015-11-02 18:20:51 +0000
commit0b296d380807050cee0a682caf388d6d71aef435 (patch)
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ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.
Incorrect value causes clock inaccuracy as huge as 1/60. Signed-off-by: Dmitry Ivanov <dima@ubnt.com> Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 47363
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