library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

entity spdif is
    port (
        xtal_50mhz : in std_logic;
        spdif_in   : in std_logic;
        n_rst_in   : in std_logic;

        n_leds     : out std_logic_vector(2 downto 0);
        n_mute_out : out std_logic;
        n_stby_out : out std_logic;

        dbg1 : out std_logic;
        dbg2 : out std_logic;
        dbg3 : out std_logic;
        dbg4 : out std_logic;
        dbg5 : out std_logic;
        dbg6 : out std_logic;
        dbg7 : out std_logic;
        dbg8 : out std_logic
        );
end spdif;


architecture rtl of spdif is
    component ccd is
        port
            (
                n_reset : in  std_logic;
                clk     : in  std_logic;
                d       : in  std_logic;
                q       : out std_logic
                );
    end component;

    component pll100 is
        port (
            areset : in  std_logic := '0';
            inclk0 : in  std_logic := '0';
            c0     : out std_logic;
            locked : out std_logic
            );
    end component;
    component pll200 is
        port (
            areset : in  std_logic := '0';
            inclk0 : in  std_logic := '0';
            c0     : out std_logic;
            locked : out std_logic
            );
    end component;
    component counter is
        port
            (
                divisor : in  std_logic_vector (15 downto 0);
                clk     : in  std_logic;
                n_reset : in  std_logic;
                clk_out : out std_logic
                );
    end component;


    component spdif_decoder is
        port
            (
                n_reset   : in  std_logic;
                clk       : in  std_logic;
                spdif     : in  std_logic;
                bmc_ready : out std_logic;
                bmc_e     : out std_logic;
                bmc_l     : out std_logic;
                bmc_d     : out std_logic;
                sof       : out std_logic;
                bna       : out std_logic;
                d         : out std_logic_vector(26 downto 0);
                ready     : out std_logic
                );
    end component;

    signal n_reset :
        std_logic;
    signal clk_200mhz :
        std_logic;
--    signal clk_100mhz :
--        std_logic;
    signal spdif_clkd1 :
        std_logic;
    signal clk1 :
        std_logic;
    signal d1   : std_logic_vector(26 downto 0);
    signal bna1 : std_logic;
    signal sof1 : std_logic;

begin
    n_reset <= n_rst_in;


    pll1 :
        pll200 port map (
            areset => not n_reset,
            inclk0 => xtal_50mhz,
            c0     => clk_200mhz
            );

--    pll2 :
--        pll200 port map (
--            areset => not n_reset,
--            inclk0 => xtal_50mhz,
--            c0     => clk_100mhz
--            );

    div1 : counter port map (
        n_reset => n_reset,
        clk     => clk_200mhz,
        divisor => x"000c",
        clk_out => clk1
        );

    b1 :
        ccd port map (
            n_reset => n_reset,
            clk     => clk1,
            d       => spdif_in,
            q       => spdif_clkd1
            );

    dec1 : spdif_decoder port map (
        n_reset   => n_reset,
        clk       => clk1,
        spdif     => spdif_clkd1,
        bmc_ready => dbg3,
        bmc_e     => dbg4,
        bmc_l     => dbg5,
        bmc_d     => dbg6,
        bna       => bna1,
        d         => d1,
        ready     => dbg7
        );

    dbg8 <= bna1;


    dbg1 <= spdif_clkd1;
    dbg2 <= clk1;


    n_leds(0) <= d1(9);
    n_leds(1) <= d1(10);
    n_leds(2) <= d1(11);

    n_mute_out <= '0';
    n_stby_out <= '0';

end rtl;