library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

entity spdif is
    port (
        xtal_50mhz : in std_logic;
        spdif_in   : in std_logic;
        n_rst_in   : in std_logic;

        led_r      : out std_logic;
        led_g      : out std_logic;
        n_leds     : out std_logic_vector(2 downto 0);
        n_mute_out : out std_logic;
        n_stby_out : out std_logic;
        dbg        : out std_logic_vector(7 downto 0)

        );
end spdif;


architecture rtl of spdif is

    component detector is
        port (
            clk_in        : in  std_logic;
            spdif_in      : in  std_logic;
            n_reset       : in  std_logic;
            divisor       : in  integer;
            silent_thresh : in  integer;
            valid_divisor : in  integer;
            valid_thresh  : in  integer;
            mute          : out std_logic;
            dbg           : out std_logic_vector(7 downto 0)
            );
    end component;

    component pll100 is
        port (
            areset : in  std_logic := '0';
            inclk0 : in  std_logic := '0';
            c0     : out std_logic;
            locked : out std_logic
            );
    end component;
    component pll200 is
        port (
            areset : in  std_logic := '0';
            inclk0 : in  std_logic := '0';
            c0     : out std_logic;
            locked : out std_logic
            );
    end component;

    signal n_reset :
        std_logic;
    signal clk_200mhz :
        std_logic;
--    signal clk_100mhz :
--        std_logic;

    signal mute1 : std_logic;
    signal mute2 : std_logic;
    signal mute3 : std_logic;
    signal mute  : std_logic;

begin
    n_reset <= n_rst_in;


    pll1 :
        pll200 port map (
            areset => not n_reset,
            inclk0 => xtal_50mhz,
            c0     => clk_200mhz
            );

    -- 96000Hz
--    det1 : detector port map (
--        n_reset  => n_reset,
--        clk_in   => clk_200mhz,
--        spdif_in => spdif_in,
--
--        divisor       => 2,  -- divisor to turn clk_in into 6x spdif base frequency
--        silent_thresh => 96000,  -- number of samples of same sample before we declare silence
--        valid_divisor => 100000000,  --  (clk_in/(divisor*valid_divisor)) is period for validity checks
--        valid_thresh  => 90000,  -- number of valid samples that must be received in validity period to declare it's all ok.
--
--        mute => mute1
--        );


    -- 44100Hz
    det2 : detector port map (
        n_reset  => n_reset,
        clk_in   => clk_200mhz,
        spdif_in => spdif_in,

        divisor       => 5,  -- divisor to turn clk_in into 6x spdif base frequency
        silent_thresh => 44100,  -- number of samples of same sample before we declare silence
        valid_divisor => 40000000,  --  (clk_in/(divisor*valid_divisor)) is period for validity checks
        valid_thresh  => 40000,  -- number of valid samples that must be received in validity period to declare it's all ok.

        mute => mute2,
        dbg  => dbg
        );

    -- 32000Hz
--    det3 : detector port map (
--        n_reset  => n_reset,
--        clk_in   => clk_200mhz,
--        spdif_in => spdif_in,
--
--        divisor       => 8,  -- divisor to turn clk_in into 6x spdif base frequency
--        silent_thresh => 32000,  -- number of samples of same sample before we declare silence
--        valid_divisor => 25000000,  --  (clk_in/(divisor*valid_divisor)) is period for validity checks
--        valid_thresh  => 30000,  -- number of valid samples that must be received in validity period to declare it's all ok.
--
--        mute => mute3
--        );

    mute1 <= '1';
    mute3 <= '1';
    mute  <= mute1 and mute2 and mute3;

    n_mute_out <= not mute;
    n_stby_out <= not mute;

    n_leds(0) <= mute1;
    n_leds(1) <= mute2;
    n_leds(2) <= mute3;

    led_r <= mute;
    led_g <= not mute;



end rtl;