#
# Design Timing Constraints Definitions
#

set_time_format -unit ns -decimal_places 3

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# Create Input reference clocks
create_clock -name {xtal_50mhz} -period 20.000 -waveform { 0.000 10.000 } [get_ports { xtal_50mhz }]
create_clock -name {det1_clk} -period 10.000 -waveform { 0.000 5.000 } [get_nets { det1|divider:div1|q }]
create_clock -name {det2_clk} -period 25.000 -waveform { 0.000 12.500 } [get_nets { det2|divider:div1|q }]
create_clock -name {det3_clk} -period 40.000 -waveform { 0.000 20.000 } [get_nets { det3|divider:div1|q }]

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# Now that we have created the custom clocks which will be base clocks,
# derive_pll_clock is used to calculate all remaining clocks for PLLs
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty