library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.numeric_std.all; entity divider is port ( divisor : in integer; clk : in std_logic; n_reset : in std_logic; clk_out : out std_logic ); end divider; architecture rtl of divider is component counter is port ( divisor : in integer; clk : in std_logic; n_reset : in std_logic; pulse_out : out std_logic ); end component; signal pulse : std_logic; signal q : std_logic; begin clk_out <= q; c1 : counter port map ( divisor => divisor, clk => clk, n_reset => n_reset, pulse_out => pulse ); process (clk, pulse, n_reset) begin if n_reset = '0' then q <= '0'; elsif RISING_EDGE(clk) and pulse = '1' then q <= not q; end if; end process; end rtl;