library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

entity dflipflop is
    port
        (
            n_reset : in  std_logic;
            clk     : in  std_logic;
            d       : in  std_logic;
            q       : out std_logic
            );
end dflipflop;


architecture rtl of dflipflop is
    signal qish :
        std_logic;
begin

    process(clk, d, n_reset)
    begin
        if n_reset = '0' then
            qish <= '0';
        elsif RISING_EDGE(clk) then
            qish <= d;
        end if;
    end process;

    q <= qish;
end rtl;