library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

entity detector is
    port (
        clk_in        : in  std_logic;
        spdif_in      : in  std_logic;
        n_reset       : in  std_logic;
        divisor       : in  integer;
        silent_thresh : in  integer;
        valid_divisor : in  integer;
        valid_thresh  : in  integer;
        mute          : out std_logic;
        dbg           : out std_logic_vector(7 downto 0)
        );
end detector;


architecture rtl of detector is
    component ccd is
        port
            (
                n_reset : in  std_logic;
                clk     : in  std_logic;
                d       : in  std_logic;
                q       : out std_logic
                );
    end component;

    component divider is
        port
            (
                divisor : in  integer;
                clk     : in  std_logic;
                n_reset : in  std_logic;
                clk_out : out std_logic
                );
    end component;

    component spdif_decoder is
        port (
            n_reset : in std_logic;
            spdif   : in std_logic;
            clk     : in std_logic;

            bmc_ready : out std_logic;
            bmc_e     : out std_logic;
            bmc_l     : out std_logic;
            bmc_d     : out std_logic;

            d     : out std_logic_vector(26 downto 0);
            ready : out std_logic;
            sof   : out std_logic;
            bna   : out std_logic;
            sos   : out std_logic
            );





    end component;


    component silence_detector is
        port
            (
                silent_thresh : in integer;
                valid_thresh  : in integer;
                valid_divisor : in integer;

                clk     : in  std_logic;
                sos     : in  std_logic;
                d       : in  std_logic_vector(23 downto 0);
                n_reset : in  std_logic;
                silent  : out std_logic;
                valid   : out std_logic;
                dbg     : out std_logic
                );
    end component;

    signal spdif :
        std_logic;
    signal clk :
        std_logic;
    signal d        : std_logic_vector(26 downto 0);
    signal sos      : std_logic;
    signal valid    : std_logic;
    signal silent   : std_logic;
    signal mute_buf : std_logic;

begin
    div1 : divider port map (
        n_reset => n_reset,
        clk     => clk_in,
        divisor => divisor,
        clk_out => clk
        );

    b :
        ccd port map (
            n_reset => n_reset,
            clk     => clk,
            d       => spdif_in,
            q       => spdif
            );

    dec : spdif_decoder port map (
        n_reset   => n_reset,
        clk       => clk,
        spdif     => spdif,
        d         => d,
        sos       => sos,
        bmc_ready => dbg(2)
        );

    sd : silence_detector port map(
        n_reset => n_reset,
        clk     => clk,
        sos     => sos,
        d       => d(26 downto 3),

        silent_thresh => silent_thresh,
        valid_thresh  => valid_thresh,
        valid_divisor => valid_divisor,

        silent => silent,
        valid  => valid,
        dbg    => dbg(7)
        );


    dbg(0) <= clk;
    dbg(1) <= spdif;
    dbg(3) <= sos;
    dbg(4) <= silent;
    dbg(5) <= valid;
    dbg(6) <= mute_buf;

    mute_buf <= silent or (not valid);

    mute <= mute_buf;

end rtl;