library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;


-- clk wants to be so that the small feature is 3 ticks

entity bmc_decoder is
    port
        (
            n_reset : in  std_logic;
            clk     : in  std_logic;
            spdif   : in  std_logic;
            ready   : out std_logic;
            e       : out std_logic;
            d       : out std_logic;
            l       : out std_logic
            );
end bmc_decoder;


architecture rtl of bmc_decoder is
    signal last_spdif   : std_logic;
    signal edge         : std_logic;
    signal ticks        : std_logic_vector(7 downto 0);
    signal last_was_one : std_logic;
    signal ready_buf    : std_logic;
begin

    edge <= last_spdif xor spdif;

    process(n_reset, clk, spdif, edge, ticks)
    begin
        if n_reset = '0' then
            ticks        <= (others => '0');
            last_was_one <= '0';
            ready_buf    <= '0';
        elsif rising_edge(clk) then
            last_spdif <= spdif;

            if edge = '1' then
                ticks <= (others => '0');
                if ticks < 1 then
                    ready_buf    <= '1';
                    e            <= '1';
                    d            <= '1';
                    l            <= '0';
                    last_was_one <= '0';
                elsif ticks < 4 then
                    if last_was_one = '0' then
                        last_was_one <= '1';
                        ready_buf    <= '1';
                        e            <= '0';
                        d            <= '1';
                        l            <= '0';
                    else
                        last_was_one <= '0';
                    end if;
                elsif ticks < 7 then
                    last_was_one <= '0';
                    ready_buf    <= '1';
                    e            <= '0';
                    l            <= '0';
                    d            <= '0';
                elsif ticks < 10 then
                    last_was_one <= '0';
                    ready_buf    <= '1';
                    e            <= '0';
                    d            <= '0';
                    l            <= '1';
                else
                    ready_buf    <= '1';
                    e            <= '1';
                    d            <= '0';
                    l            <= '1';
                    last_was_one <= '0';
                end if;
            else
                ticks     <= ticks + 1;
                ready_buf <= '0';
            end if;
        end if;
    end process;

    ready <= ready_buf;

end rtl;