From 22bcde813e924f2cca7b96941465ae0737b82fc3 Mon Sep 17 00:00:00 2001
From: root <root@no.no.james.local>
Date: Thu, 17 May 2018 17:43:06 +0100
Subject: working 3 detectors with parity checks

---
 spdif_decoder.vhd | 64 +++++++++++++++++++++++++++++++++----------------------
 1 file changed, 38 insertions(+), 26 deletions(-)

(limited to 'spdif_decoder.vhd')

diff --git a/spdif_decoder.vhd b/spdif_decoder.vhd
index d9e8a23..a8e9d94 100644
--- a/spdif_decoder.vhd
+++ b/spdif_decoder.vhd
@@ -1,6 +1,7 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.all;
 use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_misc.all;
 use IEEE.numeric_std.all;
 
 
@@ -12,22 +13,25 @@ entity spdif_decoder is
         Z32 : std_logic_vector(31 downto 0) := (others => '0')
         );
 
-    port
-        (
-            n_reset   : in  std_logic;
-            clk       : in  std_logic;
-            spdif     : in  std_logic;
-            bmc_ready : out std_logic;
-            bmc_e     : out std_logic;
-            bmc_l     : out std_logic;
-            bmc_d     : out std_logic;
-            sof       : out std_logic;
-            bna       : out std_logic;
-            d         : out std_logic_vector(26 downto 0);
-            ready     : out std_logic
-            );
-end spdif_decoder;
 
+port (
+	n_reset:in std_logic;
+	spdif:in std_logic;
+	clk:in std_logic;
+
+    bmc_ready: out std_logic;
+    bmc_e: out std_logic;
+    bmc_l: out std_logic;
+    bmc_d : out std_logic;
+	
+	d : out std_logic_vector(26 downto 0);
+	ready: out std_logic;
+	sof: out std_logic;
+	bna: out std_logic;
+	sos: out std_logic
+);
+end spdif_decoder;
+	
 
 architecture rtl of spdif_decoder is
 
@@ -50,7 +54,7 @@ architecture rtl of spdif_decoder is
     signal b_l     : std_logic;
     signal b_d     : std_logic;
 
-    signal parity : std_logic;
+    signal parity_valid : std_logic;
 
     signal e_sr : std_logic_vector(31 downto 0);
     signal d_sr : std_logic_vector(31 downto 0);
@@ -58,6 +62,7 @@ architecture rtl of spdif_decoder is
 
     signal d_buf     : std_logic_vector(26 downto 0);
     signal sof_buf   : std_logic;
+    signal sos_buf   : std_logic;
     signal ready_buf : std_logic;
     signal bna_buf   : std_logic;
 begin
@@ -95,10 +100,9 @@ begin
     end process;
 
 
--- parity<=xor_reduce(d_sr(31 downto 4));
-    parity <= '1';
+    parity_valid<= not xor_reduce(d_sr(31 downto 4));
 
-    process (clk, b_ready, e_sr, l_sr, d_sr, parity, n_reset)
+    process (clk, b_ready, e_sr, l_sr, d_sr, parity_valid, n_reset)
     begin
         if n_reset = '0' then
             d_buf     <= (others => '0');
@@ -106,26 +110,35 @@ begin
             bna_buf   <= '0';
             ready_buf <= '0';
         elsif rising_edge(clk) then
-            if (b_ready = '1') and (parity = '1') and (e_sr = Z32) then
-                if (d_sr(2 downto 0) = "010") and (l_sr(2 downto 0) = "101") then  --B code
+            if (b_ready = '1') and (parity_valid = '1') and (e_sr = Z32) then
+                if (d_sr(3 downto 1) = "010") and (l_sr(3 downto 1) = "101") then  --B code
                     d_buf     <= d_sr(29 downto 3);
                     sof_buf   <= '1';
+		    sos_buf   <='1';
                     bna_buf   <= '0';
                     ready_buf <= '1';
-                elsif (d_sr(2 downto 0) = "001") and (l_sr(2 downto 0) = "110") then  --M code
+                elsif (d_sr(3 downto 1) = "100") and (l_sr(3 downto 1) = "011") then  --M code
                     d_buf     <= d_sr(29 downto 3);
                     sof_buf   <= '0';
+		    sos_buf   <='1';
                     bna_buf   <= '0';
                     ready_buf <= '1';
-                elsif (d_sr(3 downto 0) = "0010") and (l_sr(3 downto 0) = "1000") then  --W code
+                elsif (d_sr(3 downto 0) = "0100") and (l_sr(3 downto 0) = "0001") then  --W code
                     d_buf     <= d_sr(30 downto 4);
                     sof_buf   <= '0';
+		    sos_buf   <='0';
                     bna_buf   <= '1';
                     ready_buf <= '1';
                 else
-                    ready_buf <= '0';
+                sof_buf   <= '0';
+		sos_buf   <='0';
+                bna_buf   <= '1';
+                ready_buf <= '0';
                 end if;
             else
+                sof_buf   <= '0';
+		sos_buf   <='0';
+                bna_buf   <= '1';
                 ready_buf <= '0';
             end if;
         end if;
@@ -136,8 +149,7 @@ begin
     ready <= ready_buf;
     sof   <= sof_buf;
     bna   <= bna_buf;
-
-
+    sos   <= sos_buf;
 
 end rtl;
 
-- 
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