From 7ab8f32168e55169c605c1a66446091f533ccdad Mon Sep 17 00:00:00 2001 From: Rob Langley Date: Tue, 29 May 2018 14:47:31 +0100 Subject: Just one freq supported --- spdif.vhd | 52 +++++++++++++++++++++++++++------------------------- 1 file changed, 27 insertions(+), 25 deletions(-) (limited to 'spdif.vhd') diff --git a/spdif.vhd b/spdif.vhd index 0339bad..ce2f584 100644 --- a/spdif.vhd +++ b/spdif.vhd @@ -75,18 +75,18 @@ begin ); -- 96000Hz - det1 : detector port map ( - n_reset => n_reset, - clk_in => clk_200mhz, - spdif_in => spdif_in, - - divisor => 2, -- divisor to turn clk_in into 6x spdif base frequency - silent_thresh => 96000, -- number of samples of same sample before we declare silence - valid_divisor => 100000000, -- (clk_in/(divisor*valid_divisor)) is period for validity checks - valid_thresh => 90000, -- number of valid samples that must be received in validity period to declare it's all ok. - - mute => mute1 - ); +-- det1 : detector port map ( +-- n_reset => n_reset, +-- clk_in => clk_200mhz, +-- spdif_in => spdif_in, +-- +-- divisor => 2, -- divisor to turn clk_in into 6x spdif base frequency +-- silent_thresh => 96000, -- number of samples of same sample before we declare silence +-- valid_divisor => 100000000, -- (clk_in/(divisor*valid_divisor)) is period for validity checks +-- valid_thresh => 90000, -- number of valid samples that must be received in validity period to declare it's all ok. +-- +-- mute => mute1 +-- ); -- 44100Hz @@ -105,19 +105,21 @@ begin ); -- 32000Hz - det3 : detector port map ( - n_reset => n_reset, - clk_in => clk_200mhz, - spdif_in => spdif_in, - - divisor => 8, -- divisor to turn clk_in into 6x spdif base frequency - silent_thresh => 32000, -- number of samples of same sample before we declare silence - valid_divisor => 25000000, -- (clk_in/(divisor*valid_divisor)) is period for validity checks - valid_thresh => 30000, -- number of valid samples that must be received in validity period to declare it's all ok. - - mute => mute3 - ); - +-- det3 : detector port map ( +-- n_reset => n_reset, +-- clk_in => clk_200mhz, +-- spdif_in => spdif_in, +-- +-- divisor => 8, -- divisor to turn clk_in into 6x spdif base frequency +-- silent_thresh => 32000, -- number of samples of same sample before we declare silence +-- valid_divisor => 25000000, -- (clk_in/(divisor*valid_divisor)) is period for validity checks +-- valid_thresh => 30000, -- number of valid samples that must be received in validity period to declare it's all ok. +-- +-- mute => mute3 +-- ); + + mute1 <= '1'; + mute3 <= '1'; mute <= mute1 and mute2 and mute3; n_mute_out <= not mute; -- cgit v1.2.3