From 22bcde813e924f2cca7b96941465ae0737b82fc3 Mon Sep 17 00:00:00 2001
From: root <root@no.no.james.local>
Date: Thu, 17 May 2018 17:43:06 +0100
Subject: working 3 detectors with parity checks

---
 silence_detector.vhd | 74 +++++++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 62 insertions(+), 12 deletions(-)

(limited to 'silence_detector.vhd')

diff --git a/silence_detector.vhd b/silence_detector.vhd
index fe85824..5556e68 100644
--- a/silence_detector.vhd
+++ b/silence_detector.vhd
@@ -8,47 +8,97 @@ use IEEE.numeric_std.all;
 entity silence_detector is
     port
         (
-            max_ticks : in  integer;
+            silent_thresh : in  integer;
+            valid_thresh : in  integer;
+	    valid_divisor : in integer;
+
             clk       : in  std_logic;
+	    sos		: in std_logic;
             d         : in  std_logic_vector(23 downto 0);
             n_reset   : in  std_logic;
-            silent    : out std_logic
+            silent    : out std_logic;
+            valid    : out std_logic;
+            dbg    : out std_logic
             );
 end silence_detector;
 
 
 architecture rtl of silence_detector is
 
-    signal ticks      : std_logic_vector (31 downto 0);
+    component counter is
+        port
+            (
+                divisor : in  integer;
+                clk     : in  std_logic;
+                n_reset : in  std_logic;
+                pulse_out : out std_logic
+                );
+    end component;
+
+
+    signal silence      : std_logic_vector (31 downto 0);
     signal last_d     : std_logic_vector (23 downto 0);
     signal silent_buf : std_logic;
+    signal valid_buf : std_logic;
 
+    signal validity    :  std_logic_vector(31 downto 0);
+
+    signal interval : std_logic;
 begin
 
-    process (last_d, d, clk, max_ticks, ticks)
+    vcnt : counter port map (
+        n_reset => n_reset,
+        clk     => clk,
+        divisor => valid_divisor,
+        pulse_out =>interval
+        );
+
+    process (last_d, d, clk, sos, silent_thresh, silence)
     begin
         if n_reset = '0' then
-            ticks      <= (others => '0');
-            silent_buf <= '0';
-            last_d     <= (others => '0');
-        elsif rising_edge(clk) then
+            silence      <= (others => '0');
+            silent_buf   <= '0';
+            last_d       <= (others => '0');
+        elsif rising_edge(clk)  and sos='1' then
             last_d <= d;
-
             if last_d = d then
-                if ticks < max_ticks then
-                    ticks <= ticks +1;
+                if silence < silent_thresh then
+                    silence <= silence +1;
                 else
                     silent_buf <= '1';
                 end if;
             else
-                ticks      <= (others => '0');
+                silence      <= (others => '0');
                 silent_buf <= '0';
             end if;
         end if;
     end process;
 
+    process (clk, sos, interval,  valid_thresh,validity )
+    begin
+        if n_reset = '0' then
+            validity      <= (others => '0');
+            valid_buf   <= '0';
+        elsif rising_edge(clk) then
+	   if interval='1' then
+
+		validity <= (others => '0');
+		if validity > valid_thresh then
+			valid_buf <='1';
+		else		
+			valid_buf <='0';
+		end if;
+	    elsif sos='1' then
+		validity <= validity + 1;
+	    end if;
+          end if;
+      end process;
 
     silent <= silent_buf;
+    valid <= valid_buf;
+
+    dbg<=interval;
+    
 
 end rtl;
 
-- 
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