From 3769dd04597e39140755bd4b92023570e6fcde3c Mon Sep 17 00:00:00 2001
From: James <31272717+gpd-pocket-hacker@users.noreply.github.com>
Date: Thu, 17 May 2018 17:46:40 +0100
Subject: tidy

---
 detector.vhd | 108 +++++++++++++++++++++++++++++------------------------------
 1 file changed, 54 insertions(+), 54 deletions(-)

(limited to 'detector.vhd')

diff --git a/detector.vhd b/detector.vhd
index b6e598f..c97ecd3 100644
--- a/detector.vhd
+++ b/detector.vhd
@@ -5,15 +5,15 @@ use IEEE.numeric_std.all;
 
 entity detector is
     port (
-	clk_in	:	in std_logic;
-	spdif_in:	in std_logic;
-        n_reset   : in std_logic;
-	divisor : in integer;
-        silent_thresh : in integer;
-	valid_divisor: in integer;
-        valid_thresh : in integer;
-	mute : out std_logic;
-	dbg:out std_logic_vector(7 downto 0)
+        clk_in        : in  std_logic;
+        spdif_in      : in  std_logic;
+        n_reset       : in  std_logic;
+        divisor       : in  integer;
+        silent_thresh : in  integer;
+        valid_divisor : in  integer;
+        valid_thresh  : in  integer;
+        mute          : out std_logic;
+        dbg           : out std_logic_vector(7 downto 0)
         );
 end detector;
 
@@ -40,23 +40,23 @@ architecture rtl of detector is
     end component;
 
     component spdif_decoder is
-port (
-	n_reset:in std_logic;
-	spdif:in std_logic;
-	clk:in std_logic;
+        port (
+            n_reset : in std_logic;
+            spdif   : in std_logic;
+            clk     : in std_logic;
+
+            bmc_ready : out std_logic;
+            bmc_e     : out std_logic;
+            bmc_l     : out std_logic;
+            bmc_d     : out std_logic;
+
+            d     : out std_logic_vector(26 downto 0);
+            ready : out std_logic;
+            sof   : out std_logic;
+            bna   : out std_logic;
+            sos   : out std_logic
+            );
 
-    bmc_ready: out std_logic;
-    bmc_e: out std_logic;
-    bmc_l: out std_logic;
-    bmc_d : out std_logic;
-	
-	d : out std_logic_vector(26 downto 0);
-	ready: out std_logic;
-	sof: out std_logic;
-	bna: out std_logic;
-	sos: out std_logic
-);
-	
 
 
 
@@ -65,31 +65,31 @@ port (
 
 
     component silence_detector is
-    port
-        (
-            silent_thresh : in  integer;
-            valid_thresh : in  integer;
-	    valid_divisor : in integer;
-
-            clk       : in  std_logic;
-	    sos		: in std_logic;
-            d         : in  std_logic_vector(23 downto 0);
-            n_reset   : in  std_logic;
-            silent    : out std_logic;
-            valid    : out std_logic;
-	dbg:out std_logic
-            );
+        port
+            (
+                silent_thresh : in integer;
+                valid_thresh  : in integer;
+                valid_divisor : in integer;
+
+                clk     : in  std_logic;
+                sos     : in  std_logic;
+                d       : in  std_logic_vector(23 downto 0);
+                n_reset : in  std_logic;
+                silent  : out std_logic;
+                valid   : out std_logic;
+                dbg     : out std_logic
+                );
     end component;
 
     signal spdif :
         std_logic;
     signal clk :
         std_logic;
-    signal d     : std_logic_vector(26 downto 0);
-    signal sos   : std_logic;
-    signal valid : std_logic;
-    signal silent:std_logic;
-    signal mute_buf:std_logic;
+    signal d        : std_logic_vector(26 downto 0);
+    signal sos      : std_logic;
+    signal valid    : std_logic;
+    signal silent   : std_logic;
+    signal mute_buf : std_logic;
 
 begin
     div1 : divider port map (
@@ -112,23 +112,23 @@ begin
         clk       => clk,
         spdif     => spdif,
         d         => d,
-	sos	  => sos,
-	bmc_ready => dbg(2)
+        sos       => sos,
+        bmc_ready => dbg(2)
         );
 
     sd : silence_detector port map(
-        n_reset   => n_reset,
-        clk       => clk,
-        sos	  => sos,
-        d         => d(26 downto 3),
+        n_reset => n_reset,
+        clk     => clk,
+        sos     => sos,
+        d       => d(26 downto 3),
 
         silent_thresh => silent_thresh,
         valid_thresh  => valid_thresh,
-	valid_divisor => valid_divisor,
+        valid_divisor => valid_divisor,
 
-        silent    => silent,
-	valid	  => valid,
-        dbg     => dbg(7)
+        silent => silent,
+        valid  => valid,
+        dbg    => dbg(7)
         );
 
 
-- 
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