From 0780df86a9ec88bf8810f7fef1d241030dc1b655 Mon Sep 17 00:00:00 2001 From: fishsoupisgood Date: Thu, 17 May 2018 09:17:21 +0100 Subject: first version for rob - supports only 44.1kHz --- ccd.vhd | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 ccd.vhd (limited to 'ccd.vhd') diff --git a/ccd.vhd b/ccd.vhd new file mode 100644 index 0000000..966369f --- /dev/null +++ b/ccd.vhd @@ -0,0 +1,49 @@ + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.numeric_std.all; + +entity ccd is + port + ( + n_reset : in std_logic; + clk : in std_logic; + d : in std_logic; + q : out std_logic + ); +end ccd; + + +architecture rtl of ccd is + + component dflipflop is + port ( + n_reset : in std_logic; + clk : in std_logic; + d : in std_logic; + q : out std_logic + ); + end component; + + signal d1 : + std_logic; +begin + + dff1 : + dflipflop port map ( + n_reset => n_reset, + d => d, + clk => clk, + q => d1 + ); + dff2 : + dflipflop port map ( + n_reset => n_reset, + d => d1, + clk => not clk, + q => q + ); + +end rtl; -- cgit v1.2.3