From 0780df86a9ec88bf8810f7fef1d241030dc1b655 Mon Sep 17 00:00:00 2001
From: fishsoupisgood <github@madingley.org>
Date: Thu, 17 May 2018 09:17:21 +0100
Subject: first version for rob - supports only 44.1kHz

---
 Makefile | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)
 create mode 100644 Makefile

(limited to 'Makefile')

diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..2373f0c
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,70 @@
+PROJ=spdif
+
+SRCS=$(wildcard *.vhd *.v *.qsf *.qpf )
+TIDY_SRC= bmc_decoder.vhd ccd.vhd clock_recovery.vhd counter.vhd dflipflop.vhd spdif_decoder.vhd spdif.vhd
+
+SOF=${PROJ}.sof
+POF=${PROJ}.pof
+JIC=${PROJ}.jic
+
+default: load_sof.stamp sim.stamp
+
+
+
+sta.stamp:asm.stamp
+	tools/wrap quartus_sta ${PROJ} -c ${PROJ}
+	touch $@
+
+asm.stamp:fit.stamp
+	tools/wrap quartus_asm --read_settings_files=off --write_settings_files=off ${PROJ} -c ${PROJ}
+	touch $@
+
+${POF} ${SOF}:asm.stamp
+
+fit.stamp: ans.stamp
+	tools/wrap quartus_fit --read_settings_files=off --write_settings_files=off ${PROJ} -c ${PROJ}
+	touch $@
+
+ans.stamp: ${SRCS}
+	tools/wrap quartus_map --read_settings_files=on --write_settings_files=off ${PROJ} -c ${PROJ}
+	touch $@
+
+sim.stamp: fit.stamp
+	tools/wrap quartus_eda ${PROJ} --simulation --tool=modelsim --format=verilog
+
+
+load_sof.stamp: ${SOF}
+	tools/wrap quartus_pgm -m JTAG -o "p;${SOF}"
+
+#flash: ${POF}
+#	tools/wrap quartus_pgm -m AS -o "p;${POF}"
+
+quartus:
+	tools/wrap quartus ${PROJ}.qpf
+
+jtagd:
+	sudo killall jtagd || true
+	sudo tools/wrap jtagd
+
+clean:
+	/bin/rm -rf ${BSP_DIR} db incremental_db src/obj simulation output_files
+	/bin/rm -f ${SOPC_FILE} src/Makefile elf.flash sof.flash *.stamp ${SOF} ${ELF} *.rpt *.html *.summary *.pin *.jdi *.qws *.pof *.smsg
+	/bin/rm -f src/${PROJ}.objdump src/${PROJ}.map 
+	/bin/rm -f sopc_builder_log.txt src/*~ SDIF/*~
+	/bin/rm -f sim.stamp  *.orig
+	
+	
+
+${JIC}:${SOF}
+	tools/wrap quartus_cpf -c ${PROJ}.cof
+
+
+flash:${JIC}
+	tools/wrap quartus_pgm -m JTAG -o "ip;${JIC}"
+	tools/wrap quartus_pgm -m JTAG -o "p;${SOF}"
+
+	
+
+tidy:
+	for i in ${TIDY_SRC}; do tools/vhdl-pretty < $$i > $$i.pp && mv -f $$i $$i.orig && mv $$i.pp $$i ; done
+
-- 
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