From 741560238b27473cd9faa4e52abc55baa868ee27 Mon Sep 17 00:00:00 2001
From: fishsoupisgood <github@madingley.org>
Date: Thu, 17 May 2018 23:19:20 +0100
Subject: only use +ve clock edges

---
 ccd.vhd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ccd.vhd b/ccd.vhd
index 966369f..c4e66ad 100644
--- a/ccd.vhd
+++ b/ccd.vhd
@@ -42,7 +42,7 @@ begin
         dflipflop port map (
             n_reset => n_reset,
             d       => d1,
-            clk     => not clk,
+            clk     => clk,
             q       => q
             );
 
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